On Tue, 29 Aug 2023 at 17:00, Praveenkumar I <quic_ipkumar@xxxxxxxxxxx> wrote:
>
> Add ipq5332 USB3 SS UNIPHY support.
>
> Signed-off-by: Praveenkumar I <quic_ipkumar@xxxxxxxxxxx>
> ---
> .../devicetree/bindings/phy/qcom,uniphy.yaml | 117 +++++++++++++++++-
> 1 file changed, 114 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom,uniphy.yaml b/Documentation/devicetree/bindings/phy/qcom,uniphy.yaml
> index cbe2cc820009..17ba661b3d9b 100644
> --- a/Documentation/devicetree/bindings/phy/qcom,uniphy.yaml
> +++ b/Documentation/devicetree/bindings/phy/qcom,uniphy.yaml
> @@ -19,21 +19,53 @@ properties:
> enum:
> - qcom,usb-ss-ipq4019-phy
> - qcom,usb-hs-ipq4019-phy
> + - qcom,ipq5332-usb-ssphy
>
> reg:
> maxItems: 1
>
> + reg-names:
> + items:
> + - const: phy_base
> +
> + clocks:
> + maxItems: 3
> +
> + clock-names:
> + maxItems: 3
> +
> + "#clock-cells":
> + const: 0
> +
> resets:
> + minItems: 1
> maxItems: 2
>
> reset-names:
> - items:
> - - const: por_rst
> - - const: srif_rst
> + minItems: 1
> + maxItems: 2
> +
> + clock-output-names:
> + maxItems: 1
>
> "#phy-cells":
> const: 0
>
> + qcom,phy-mux-sel:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description:
> + PHY Mux Selection for used to select which interface is going to use the
> + combo PHY.
> + items:
> + - items:
> + - description: phandle to TCSR syscon region
> + - description: offset to the PHY Mux selection register
> + - description: value to write on the PHY Mux selection register
Generally these values should be a part of the driver, since they are
specific to the particular SoC, rather than being different from
device to device.
> +
> + vdd-supply:
> + description:
> + Phandle to 5V regulator supply to PHY digital circuit.
> +
> required:
> - compatible
> - reg
> @@ -41,6 +73,68 @@ required:
> - reset-names
> - "#phy-cells"
>
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,ipq5332-usb-ssphy
> + then:
> + properties:
> + clocks:
> + maxItems: 3
> + clock-names:
> + items:
> + - const: pipe
> + - const: phy_cfg_ahb
> + - const: phy_ahb
> +
> + "#clock-cells":
> + const: 0
> +
> + clock-output-names:
> + maxItems: 1
> +
> + resets:
> + maxItems: 1
> + reset-names:
> + items:
> + - const: por_rst
> +
> + vdda-supply:
> + description:
> + Phandle to 5V regulator supply to PHY digital circuit.
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,usb-ss-ipq4019-phy
> + then:
> + properties:
> + resets:
> + maxItems: 1
> + reset-names:
> + items:
> + - const: por_rst
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,usb-hs-ipq4019-phy
> + then:
> + properties:
> + resets:
> + maxItems: 2
> + reset-names:
> + items:
> + - const: por_rst
> + - const: srif_rst
> +
> additionalProperties: false
>
> examples:
> @@ -55,3 +149,20 @@ examples:
> <&gcc USB2_HSPHY_S_ARES>;
> reset-names = "por_rst", "srif_rst";
> };
> +
> + - |
> + #include <dt-bindings/clock/qcom,ipq5332-gcc.h>
> +
> + ssuniphy@4b0000 {
> + #phy-cells = <0>;
> + #clock-cells = <0>;
> + compatible = "qcom,ipq5332-usb-ssphy";
> + reg = <0x4b0000 0x800>;
> + clocks = <&gcc GCC_USB0_PIPE_CLK>,
> + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE3X1_PHY_AHB_CLK>;
> + clock-names = "pipe", "phy_cfg_ahb", "phy_ahb";
> +
> + resets = <&gcc GCC_USB0_PHY_BCR>;
> + reset-names = "por_rst";
> + };
> --
> 2.34.1
>
--
With best wishes
Dmitry
