Re: [PATCH 10/11] usb: dwc3: dwc3-octeon: Move node parsing into driver probe

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On Sun, Jul 02, 2023, Ladislav Michl wrote:
> Hi,
> 
> thank you for review, v2 is about to be sent, here just let
> me anwer issue I didn't address there.
> 
> On Fri, Jun 30, 2023 at 11:27:37PM +0000, Thinh Nguyen wrote:
> > On Mon, Jun 19, 2023, Ladislav Michl wrote:
> [snip]
> > > +	ref_clk_sel = 2;
> > 
> > Can we use macro instead of magic numbers?
> 
> This is a bit problematic, comment above USBDRD_UCTL_CTL_REF_CLK_SEL
> says:
> /* Reference clock select for SuperSpeed and HighSpeed PLLs:
>  *      0x0 = Both PLLs use DLMC_REF_CLK0 for reference clock
>  *      0x1 = Both PLLs use DLMC_REF_CLK1 for reference clock
>  *      0x2 = SuperSpeed PLL uses DLMC_REF_CLK0 for reference clock &
>  *            HighSpeed PLL uses PLL_REF_CLK for reference clck
>  *      0x3 = SuperSpeed PLL uses DLMC_REF_CLK1 for reference clock &
>  *            HighSpeed PLL uses PLL_REF_CLK for reference clck
>  */
> So I really cannot imagine sane name. Also please note, that field
> and register names were created to match documentation. Values,
> however, have no defined names, so I would need to invent them.
> That is something I'd like to avoid as it might be confusing.
> 
> And last, but to least: Octeon would deserve proper clock api
> (clk driver to be implemented). So hopefully that code get
> replaced with more sane one. For now, I just kept compatibility
> with current DT.
> 
> Thanks,
> 	ladis

Sure. That's reasonable.

Thanks,
Thinh




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