On Sun, Jun 04, 2023 at 03:11:43PM -0500, Corey Minyard wrote: > On Sun, Jun 04, 2023 at 02:17:16PM +0200, Johan Hovold wrote: > > I just verified break signalling on the first port of my CP2105 using a > > logic analyser and everything seems to work as expected. > > > > There's also no mention of any issue with break in the errata. > > > > Could you check which firmware revision you have by enabling debugging > > and reconnecting the device? > [ 4.253869] usb 2-1.2: new full-speed USB device number 3 using ehci-pci > [ 4.342570] usb 2-1.2: New USB device found, idVendor=10c4, idProduct=ea70, bcdDevice= 1.00 > [ 4.350939] usb 2-1.2: New USB device strings: Mfr=1, Product=2, SerialNumber=5 > [ 4.358259] usb 2-1.2: Product: CP2105 Dual USB to UART Bridge Controller > [ 4.365052] usb 2-1.2: Manufacturer: Silicon Labs > [ 4.369765] usb 2-1.2: SerialNumber: 01070456 > [ 4.374925] cp210x 2-1.2:1.0: cp210x converter detected > [ 4.381086] cp210x 2-1.2:1.0: cp210x_get_fw_version - 1.18.1 > [ 4.386915] usb 2-1.2: cp210x converter now attached to ttyUSB0 > [ 4.393529] cp210x 2-1.2:1.1: cp210x converter detected > [ 4.399835] cp210x 2-1.2:1.1: cp210x_get_fw_version - 1.18.1 > [ 4.405657] usb 2-1.2: cp210x converter now attached to ttyUSB1 So we have the same firmware revision. > This is an embedded reference board, I guess there is some probability > that this is just broken on this board, though I'm not quite sure how. Is the port accessible somehow so that you could hook up a scope or logic analyser? Or is that what you did already when you mentioned seeing garbage sent after 2.5 seconds? That last bit seems to match the behaviour I see with the second, SCI port, where the last character sent is resent when trying to signal a break. Johan
