Intel Barlow Ridge Thunderbolt controller has 3 DP IN adapters. This
allows 3 simultaneus DisplayPort tunnels through either one or two USB4
downstream ports (in any possible configuration). Add test case for
this.
Signed-off-by: Mika Westerberg <mika.westerberg@xxxxxxxxxxxxxxx>
---
drivers/thunderbolt/test.c | 83 ++++++++++++++++++++++++++++++++++++++
1 file changed, 83 insertions(+)
diff --git a/drivers/thunderbolt/test.c b/drivers/thunderbolt/test.c
index 24c06e7354cd..9475c6698c7d 100644
--- a/drivers/thunderbolt/test.c
+++ b/drivers/thunderbolt/test.c
@@ -170,6 +170,23 @@ static struct tb_switch *alloc_host_usb4(struct kunit *test)
return sw;
}
+static struct tb_switch *alloc_host_br(struct kunit *test)
+{
+ struct tb_switch *sw;
+
+ sw = alloc_host_usb4(test);
+ if (!sw)
+ return NULL;
+
+ sw->ports[10].config.type = TB_TYPE_DP_HDMI_IN;
+ sw->ports[10].config.max_in_hop_id = 9;
+ sw->ports[10].config.max_out_hop_id = 9;
+ sw->ports[10].cap_adap = -1;
+ sw->ports[10].disabled = false;
+
+ return sw;
+}
+
static struct tb_switch *alloc_dev_default(struct kunit *test,
struct tb_switch *parent,
u64 route, bool bonded)
@@ -1583,6 +1600,71 @@ static void tb_test_tunnel_dp_max_length(struct kunit *test)
tb_tunnel_free(tunnel);
}
+static void tb_test_tunnel_3dp(struct kunit *test)
+{
+ struct tb_switch *host, *dev1, *dev2, *dev3, *dev4, *dev5;
+ struct tb_port *in1, *in2, *in3, *out1, *out2, *out3;
+ struct tb_tunnel *tunnel1, *tunnel2, *tunnel3;
+
+ /*
+ * Create 3 DP tunnels from Host to Devices #2, #5 and #4.
+ *
+ * [Host]
+ * 3 |
+ * 1 |
+ * [Device #1]
+ * 3 / | 5 \ 7
+ * 1 / | \ 1
+ * [Device #2] | [Device #4]
+ * | 1
+ * [Device #3]
+ * | 5
+ * | 1
+ * [Device #5]
+ */
+ host = alloc_host_br(test);
+ dev1 = alloc_dev_default(test, host, 0x3, true);
+ dev2 = alloc_dev_default(test, dev1, 0x303, true);
+ dev3 = alloc_dev_default(test, dev1, 0x503, true);
+ dev4 = alloc_dev_default(test, dev1, 0x703, true);
+ dev5 = alloc_dev_default(test, dev3, 0x50503, true);
+
+ in1 = &host->ports[5];
+ in2 = &host->ports[6];
+ in3 = &host->ports[10];
+
+ out1 = &dev2->ports[13];
+ out2 = &dev5->ports[13];
+ out3 = &dev4->ports[14];
+
+ tunnel1 = tb_tunnel_alloc_dp(NULL, in1, out1, 1, 0, 0);
+ KUNIT_ASSERT_TRUE(test, tunnel1 != NULL);
+ KUNIT_EXPECT_EQ(test, tunnel1->type, TB_TUNNEL_DP);
+ KUNIT_EXPECT_PTR_EQ(test, tunnel1->src_port, in1);
+ KUNIT_EXPECT_PTR_EQ(test, tunnel1->dst_port, out1);
+ KUNIT_ASSERT_EQ(test, tunnel1->npaths, 3);
+ KUNIT_ASSERT_EQ(test, tunnel1->paths[0]->path_length, 3);
+
+ tunnel2 = tb_tunnel_alloc_dp(NULL, in2, out2, 1, 0, 0);
+ KUNIT_ASSERT_TRUE(test, tunnel2 != NULL);
+ KUNIT_EXPECT_EQ(test, tunnel2->type, TB_TUNNEL_DP);
+ KUNIT_EXPECT_PTR_EQ(test, tunnel2->src_port, in2);
+ KUNIT_EXPECT_PTR_EQ(test, tunnel2->dst_port, out2);
+ KUNIT_ASSERT_EQ(test, tunnel2->npaths, 3);
+ KUNIT_ASSERT_EQ(test, tunnel2->paths[0]->path_length, 4);
+
+ tunnel3 = tb_tunnel_alloc_dp(NULL, in3, out3, 1, 0, 0);
+ KUNIT_ASSERT_TRUE(test, tunnel3 != NULL);
+ KUNIT_EXPECT_EQ(test, tunnel3->type, TB_TUNNEL_DP);
+ KUNIT_EXPECT_PTR_EQ(test, tunnel3->src_port, in3);
+ KUNIT_EXPECT_PTR_EQ(test, tunnel3->dst_port, out3);
+ KUNIT_ASSERT_EQ(test, tunnel3->npaths, 3);
+ KUNIT_ASSERT_EQ(test, tunnel3->paths[0]->path_length, 3);
+
+ tb_tunnel_free(tunnel2);
+ tb_tunnel_free(tunnel1);
+}
+
static void tb_test_tunnel_usb3(struct kunit *test)
{
struct tb_switch *host, *dev1, *dev2;
@@ -2790,6 +2872,7 @@ static struct kunit_case tb_test_cases[] = {
KUNIT_CASE(tb_test_tunnel_dp_chain),
KUNIT_CASE(tb_test_tunnel_dp_tree),
KUNIT_CASE(tb_test_tunnel_dp_max_length),
+ KUNIT_CASE(tb_test_tunnel_3dp),
KUNIT_CASE(tb_test_tunnel_port_on_path),
KUNIT_CASE(tb_test_tunnel_usb3),
KUNIT_CASE(tb_test_tunnel_dma),
--
2.39.2
