On 12/04/2023 23:59, Thinh Nguyen wrote: > On Wed, Apr 12, 2023, Roger Quadros wrote: >> >> >> On 06/04/2023 04:38, Thinh Nguyen wrote: >>> On Wed, Apr 05, 2023, Roger Quadros wrote: >>>> >>>> >>>> On 05/04/2023 00:53, Thinh Nguyen wrote: >>>>> >>>>> I may have misunderstood your platform implementation. My understanding >>>>> is that it can only detect VBUS and that it can only resume on VBUS >>>>> valid. >>>>> >>>>> Does the "LINESTATE" here gets asserted if say there's a LFPS detection? >>>> >>>> Yes. The wake up logic on the SoC is snooping the UTMI lines from the PHY and on any >>>> change it can detect and wake up the SoC. >>>> >>> >>> Are you referring to the utmi_linestate signal? Isn't that for usb2 >>> speed only? Does your platform support usb3 speed? >> >> The wake-up on deepSleep feature is only supported for USB2 on this particular SoC. >> > > I mean can your platform operate in usb3 speed. If that's the case, then > how do you plan to handle it here. No, this SoC can only support up to USB2 speed. > > Also, when you tested this in highspeed, did you observe successful > resume? Or did the host have to perform a port reset? I definitely didn't see a disconnect. Not sure about port reset. I will check and get back. cheers, -roger
