>
> On Wed, Apr 12, 2023, Stanley Chang wrote:
> > The RTK DHC SoCs were designed the global register address offset at
> > 0x8100. The default address is at DWC3_GLOBALS_REGS_START (0xc100).
> > Therefore, add the property of device-tree to adjust this start address.
> >
> > Signed-off-by: Stanley Chang <stanley_chang@xxxxxxxxxxx>
> > ---
>
> Please note what changed in v2 after the --- line. Also why did you split the
> previous series in 2 now? It'll be confusing for us maintainers.
>
Do you mean that to split the part of "remapping global register start address and
the part of " snps,parkmode-disable-hs-quirk"?
They are different series. I just submit them at the same time.
> > drivers/usb/dwc3/core.c | 18 ++++++++++++++++++
> > 1 file changed, 18 insertions(+)
> >
> > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index
> > 476b63618511..96d3e634ebbf 100644
> > --- a/drivers/usb/dwc3/core.c
> > +++ b/drivers/usb/dwc3/core.c
> > @@ -1785,6 +1785,24 @@ static int dwc3_probe(struct platform_device
> *pdev)
> > dwc_res = *res;
> > dwc_res.start += DWC3_GLOBALS_REGS_START;
> >
> > + /*
> > + * For some dwc3 controller, the dwc3 global register start address is
> > + * not at DWC3_GLOBALS_REGS_START (0xc100).
> > + */
> > + if (dev->of_node) {
> > + int global_regs_starting_offset = 0;
> > +
> > + device_property_read_u32(dev,
> "snps,global-regs-starting-offset",
> > + &global_regs_starting_offset);
>
> I suggested to use compatible string instead since this isn't common and only
> unique to your platform. Any reason we shouldn't do that?
>
> ie. something like this:
>
> if (dev->of_node && of_device_is_compatiable(dev->of_node,
> "your-platform"))
> dwc_res.start += your_platform_offset; else
> dwc_res.start = DWC3_GLOBALS_REGS_START;
>
I will try this suggestion.
Thanks,
Stanley
