The RTK DHC SoCs were designed the global register address offset at 0x8100.
The default address is at DWC3_GLOBALS_REGS_START (0xc100).
Therefore, add the property of device-tree to adjust this start address.
Signed-off-by: Stanley Chang <stanley_chang@xxxxxxxxxxx>
---
drivers/usb/dwc3/core.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 476b63618511..771b35449376 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -1785,6 +1785,23 @@ static int dwc3_probe(struct platform_device *pdev)
dwc_res = *res;
dwc_res.start += DWC3_GLOBALS_REGS_START;
+ /* For some dwc3 controller, the dwc3 global register start address is
+ * not at DWC3_GLOBALS_REGS_START (0xc100).
+ */
+ if (dev) {
+ int fixed_dwc3_globals_regs_start;
+
+ device_property_read_u32(dev, "snps,fixed_dwc3_globals_regs_start",
+ &fixed_dwc3_globals_regs_start);
+ if (fixed_dwc3_globals_regs_start) {
+ dwc_res.start -= DWC3_GLOBALS_REGS_START;
+ dwc_res.start += fixed_dwc3_globals_regs_start;
+ dev_info(dev,
+ "fixed dwc3 globals register start address from 0x%x to end 0x%x\n",
+ (int)dwc_res.start, (int)dwc_res.end);
+ }
+ }
+
regs = devm_ioremap_resource(dev, &dwc_res);
if (IS_ERR(regs))
return PTR_ERR(regs);
--
2.34.1
