On 26.3.2023 18.58, Erhard Furtner wrote:
On Mon, 20 Mar 2023 11:26:39 +0200
Mathias Nyman <mathias.nyman@xxxxxxxxxxxxxxx> wrote:
This could be related to another case with two xHC controllers, but different vendors.
Bus numbers were interleaved there as well. Removing the asynch probe helped:
https://lore.kernel.org/linux-usb/d5ff9480-57bd-2c39-8b10-988ad0d14a7e@xxxxxxxxxxxxxxx/
Does reverting:
4c2604a9a689 usb: xhci-pci: Set PROBE_PREFER_ASYNCHRONOUS
help for you?
Ok, reverted 4c2604a9a689 usb: xhci-pci: Set PROBE_PREFER_ASYNCHRONOUS now but unfortunately didn't work out. New dmesg with the reverted commit attached.
Regards,
Erhard
Closer look at dmesg shows we are stuck while trying to rest the VIA xHC during probe.
Driver times out after 10 seconds.
[ 8.306783] xhci_hcd 0000:07:00.0: xHCI Host Controller
[ 8.306791] xhci_hcd 0000:07:00.0: new USB bus registered, assigned bus number 10
[ 8.311622] xhci_hcd 0000:07:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x000e address=0xce210880 flags=0x0000]
...
[ 18.306812] xhci_hcd 0000:07:00.0: can't setup: -110
[ 18.306830] xhci_hcd 0000:07:00.0: USB bus 10 deregistered
[ 18.307005] xhci_hcd 0000:07:00.0: init 0000:07:00.0 fail, -110
There is also a IOMMU entry in the log at the same time driver starts resetting the xHC.
There have been some other hosts that triggered IOMMU issues when host tried to access a partial
64 bit DMA address immediately after driver wrote first 32 bits.
Did this VIA xHC work with any older kernel, if yes, any chance you could bisect this?
Also possible that this host would work with a 32 bit DMA mask, hack:
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index 6183ce8574b1..e5b7700a807f 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -5408,7 +5408,7 @@ int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
/* Set dma_mask and coherent_dma_mask to 64-bits,
* if xHC supports 64-bit addressing */
- if (HCC_64BIT_ADDR(xhci->hcc_params) &&
+ if (0 && HCC_64BIT_ADDR(xhci->hcc_params) &&
!dma_set_mask(dev, DMA_BIT_MASK(64))) {
xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
Thanks
Mathias
