On 06/01/2023 16:28, Jon Hunter wrote: > From: Wayne Chang <waynec@xxxxxxxxxx> > > Add device-tree binding documentation for the XUSB host controller present > on Tegra234 SoC. This controller supports the USB 3.1 specification. > > Signed-off-by: Wayne Chang <waynec@xxxxxxxxxx> > Signed-off-by: Thierry Reding <treding@xxxxxxxxxx> > Signed-off-by: Jon Hunter <jonathanh@xxxxxxxxxx> > --- > V4 -> V5: No changes > V3 -> V4: minor update to the power-domain description > V2 -> V3: nothing has changed > V1 -> V2: address the issue on phy-names property > > .../bindings/usb/nvidia,tegra234-xusb.yaml | 158 ++++++++++++++++++ > 1 file changed, 158 insertions(+) > create mode 100644 Documentation/devicetree/bindings/usb/nvidia,tegra234-xusb.yaml > > diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra234-xusb.yaml b/Documentation/devicetree/bindings/usb/nvidia,tegra234-xusb.yaml > new file mode 100644 > index 000000000000..190a23c72963 > --- /dev/null > +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra234-xusb.yaml > @@ -0,0 +1,158 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/usb/nvidia,tegra234-xusb.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NVIDIA Tegra234 xHCI controller > + > +maintainers: > + - Thierry Reding <thierry.reding@xxxxxxxxx> > + - Jon Hunter <jonathanh@xxxxxxxxxx> > + > +description: The Tegra xHCI controller supports both USB2 and USB3 interfaces Line ends after "description:" > + exposed by the Tegra XUSB pad controller. > + > +properties: > + compatible: > + const: nvidia,tegra234-xusb > + > + reg: > + items: > + - description: base and length of the xHCI host registers Just "xHCI host registers". Same in other places. > + - description: base and length of the XUSB FPCI registers > + - description: base and length of the XUSB bar2 registers > + > + reg-names: > + items: > + - const: hcd > + - const: fpci > + - const: bar2 > + > + interrupts: > + items: > + - description: xHCI host interrupt > + - description: mailbox interrupt > + > + clocks: > + items: > + - description: XUSB host clock > + - description: XUSB Falcon source clock > + - description: XUSB SuperSpeed clock > + - description: XUSB SuperSpeed source clock > + - description: XUSB HighSpeed clock source > + - description: XUSB FullSpeed clock source > + - description: USB PLL > + - description: reference clock > + - description: I/O PLL > + > + clock-names: > + items: > + - const: xusb_host > + - const: xusb_falcon_src > + - const: xusb_ss > + - const: xusb_ss_src > + - const: xusb_hs_src > + - const: xusb_fs_src > + - const: pll_u_480m > + - const: clk_m > + - const: pll_e > + > + interconnects: > + items: > + - description: read client > + - description: write client > + > + interconnect-names: > + items: > + - const: dma-mem # read > + - const: write > + > + iommus: > + maxItems: 1 > + > + nvidia,xusb-padctl: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: phandle to the XUSB pad controller that is used to configure > + the USB pads used by the XHCI controller > + > + phys: > + minItems: 1 > + maxItems: 8 > + > + phy-names: > + minItems: 1 > + maxItems: 8 > + items: > + enum: > + - usb2-0 > + - usb2-1 > + - usb2-2 > + - usb2-3 > + - usb3-0 > + - usb3-1 > + - usb3-2 > + - usb3-3 Why do you have so many optional phys? In what case you would put there usb2-0 and usb3-3 together? Or even 8 phys at the same time? IOW, what are the differences between them and why one controller would be connected once to usb3-2 and once to usb3-3 phy? And once to both? > + > + power-domains: > + items: > + - description: XUSBC power domain (for Host and USB 2.0) > + - description: XUSBA power domain (for SuperSpeed) > + > + power-domain-names: > + items: > + - const: xusb_host > + - const: xusb_ss > + > + dma-coherent: Just: true > + type: boolean Drop > + > +allOf: > + - $ref: usb-xhci.yaml > + > +unevaluatedProperties: false > + Best regards, Krzysztof
