On Tue, Oct 04, 2022 at 06:38:47AM -0500, Limonciello, Mario wrote: > On 10/4/2022 00:04, Mika Westerberg wrote: > > Hi Mario, > > > > On Mon, Oct 03, 2022 at 11:12:23PM -0500, Mario Limonciello wrote: > > > Both on Intel's and AMD's USB4 designs it's important that the device > > > link to the XHCI controller used for tunneling is able to go into D3 > > > for appropriate low power consumption features as well as for system > > > suspend states such as s0i3. > > > > > > Historically this is accomplished by adding to a hardcoded list in the > > > XHCI driver, but this requires a change for every single platform. > > > > > > We have a very good proxy that it's safe to do this since the firmware > > > has indicated the device link needs to be made. So opt all XHCI > > > controllers with these device links into runtime PM. > > > > This is good idea. > > > > However, it misses the fact that we have FW CM as well in Intel > > integrated TBT platforms (ICL, TGL and ADL) and with those you don't > > have the device link (I think ADL has it for both, though) so we would > > still need to keep the list in xHCI. > > Can you double check the firmware for ADL for me whether it has it for both? > I'll respin the series and drop at least the ICL and TGL reverts from patch Yes, ADL has it for both. While doing that, I wonder if it would be easier to understand (and follow) if all this is done in the xHCI side? It can also look for the property and unblock runtime PM based on that.
