On Fri, Aug 19, 2022 at 9:04 PM Bjorn Andersson <bjorn.andersson@xxxxxxxxxx> wrote: > > On Fri 19 Aug 17:18 CDT 2022, Prashant Malani wrote: > > > On Fri, Aug 19, 2022 at 2:39 PM Bjorn Andersson > > <bjorn.andersson@xxxxxxxxxx> wrote: > > Are you saying that two of your SS-lanes in connector A are connected to > directly to the QMP PHY at the same time as two SS-lanes from connector > B are connected to the same two pads on the QMP PHY - without any > mux etc inbetween? > > I.e. that there are a set of pins in connector A which is directly > connected to a set of pins in connector B? > > > I was under the impression that in your hardware there's some component > muxing the single DP output to one of the connectors. If so there should > be no graph-link directly connecting the two usb-c-connectors and the > one QMP PHY. > > Is this not the case? I can't speak to the QMP PHY specifically (since I'm not using that hardware), but your impression is right. There is a component (anx7625) muxing the single DP output to the 2 usb-c-connectors (specifically, 2 lanes each from the 2 usb-c-connectors). The other 2 lanes (from the 2 USB-C-connectors) go to a USB3 hub; hence the need for 2 endpoints for each usb-c-connector). So, the anx7625 should register the mode switches and it needs the graph connections from 2 usb-c-connectors BR, -Prashant
