Hi Geert and Rob, > Subject: Re: [PATCH] dt-bindings: usb: ehci: Increase the number of PHYs > > Hi Rob, > > On Wed, Jun 15, 2022 at 7:24 PM Rob Herring <robh+dt@xxxxxxxxxx> wrote: > > On Wed, Jun 15, 2022 at 7:53 AM Geert Uytterhoeven > > <geert+renesas@xxxxxxxxx> wrote: > > > > > > "make dtbs_check": > > > > > > arch/arm/boot/dts/r8a77470-iwg23s-sbc.dtb: usb@ee080100: phys: > [[17, 0], [31]] is too long > > > From schema: > Documentation/devicetree/bindings/usb/generic-ehci.yaml > > > arch/arm/boot/dts/r8a77470-iwg23s-sbc.dtb: usb@ee0c0100: phys: > [[17, 1], [33], [21, 0]] is too long > > > From schema: > > > Documentation/devicetree/bindings/usb/generic-ehci.yaml > > > > > > Some USB EHCI controllers (e.g. on the Renesas RZ/G1C SoC) have > > > multiple PHYs. Increase the maximum number of PHYs to 3, which is > > > sufficient for now. > > > > Maybe not so 'generic'. Why are there 3? I understand USB3 HCI having > > 2 for SS and HS. Is it for multiple ports? There's a thread about that > > currently (Mediatek IIRC) and how to handle multiple phys. > > TBH, I don't know for sure. I've never been much into USB, and the > RZ/G1C USB architecture differs from other Renesas SoCs in the same > family. > > This is USB2, not USB3. There are two channels of OHCI/EHCI, and two > channels of USB OTG, all with corresponding PHYs (4 in total). > The first OHCI/EHCI combo is linked to one of the host PHYs, and one of > the OTG PHYs, so that makes 2 PHYs. Yes 1 Host phy and other OTG PHY makes it 2 PHYs. > The second OHCI/EHCI combo is linked to the other host PHY, and to both > OTG PHYs, so that makes 3 PHYs. IIRC the third link was due to some > dependency between the 2 OTG PHYs. The third PHY is a dummy one to initialize timing/interrupt generation registers by reusing the phy-rcar-gen3-usb2 driver. Regards, Biju
