The USB4 1.0 specification outlines the `cap_plug_events` structure in table 13-14 located on page 507. This shows that there was a mistake in VSC_CS_1 where plug events disable should be 4 bits and "TBT3-Compatible" should be 3 bits. While correcting the mistake, update the names and comments to more closely match the specification. This should not change anything functionally. Link: https://www.usb.org/sites/default/files/USB4%20Specification%2020211116.zip Signed-off-by: Mario Limonciello <mario.limonciello@xxxxxxx> --- drivers/thunderbolt/tb_regs.h | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/thunderbolt/tb_regs.h b/drivers/thunderbolt/tb_regs.h index 70795a2aa9bb..8c42f8bc679e 100644 --- a/drivers/thunderbolt/tb_regs.h +++ b/drivers/thunderbolt/tb_regs.h @@ -146,14 +146,14 @@ struct tb_eeprom_ctl { struct tb_cap_plug_events { struct tb_cap_extended_short cap_header; - u32 __unknown1:2; - u32 plug_events:5; - u32 __unknown2:25; - u32 __unknown3; - u32 __unknown4; + u32 __unknown1:3; /* VSC_CS_1 */ + u32 plug_events:4; /* VSC_CS_1 */ + u32 __unknown2:25; /* VSC_CS_1 */ + u32 vsc_cs_2; + u32 vsc_cs_3; struct tb_eeprom_ctl eeprom_ctl; - u32 __unknown5[7]; - u32 drom_offset; /* 32 bit register, but eeprom addresses are 16 bit */ + u32 __unknown5[7]; /* VSC_CS_5 -> VSC_CS_11 */ + u32 drom_offset; /* VSC_CS_12: 32 bit register, but eeprom addresses are 16 bit */ } __packed; /* device headers */ @@ -464,6 +464,10 @@ struct tb_regs_hop { /* Plug Events registers */ #define TB_PLUG_EVENTS_USB_DISABLE BIT(2) +#define USB4_PLUG_EVENTS_LANE_DISABLE BIT(3) +#define USB4_PLUG_EVENTS_DPOUT_DISABLE BIT(4) +#define USB4_PLUG_EVENTS_LOW_DPIN_DISABLE BIT(5) +#define USB4_PLUG_EVENTS_HIGH_DPIN_DISABLE BIT(6) #define TB_PLUG_EVENTS_PCIE_WR_DATA 0x1b #define TB_PLUG_EVENTS_PCIE_CMD 0x1c -- 2.34.1
