On 1/25/2022 8:18 PM, Dinh Nguyen wrote:
> The DWC2 IP on the Agilex platform does not support clock-gating.
>
> Signed-off-by: Dinh Nguyen <dinguyen@xxxxxxxxxx>
Acked-by: Minas Harutyunyan <Minas.Harutyunyan@xxxxxxxxxxxx>
> ---
> drivers/usb/dwc2/params.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
> index d300ae3d9274..1306f4ec788d 100644
> --- a/drivers/usb/dwc2/params.c
> +++ b/drivers/usb/dwc2/params.c
> @@ -82,6 +82,14 @@ static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg)
> p->phy_utmi_width = 8;
> }
>
> +static void dwc2_set_socfpga_agilex_params(struct dwc2_hsotg *hsotg)
> +{
> + struct dwc2_core_params *p = &hsotg->params;
> +
> + p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
> + p->no_clock_gating = true;
> +}
> +
> static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg)
> {
> struct dwc2_core_params *p = &hsotg->params;
> @@ -239,6 +247,8 @@ const struct of_device_id dwc2_of_match_table[] = {
> .data = dwc2_set_stm32mp15_fsotg_params },
> { .compatible = "st,stm32mp15-hsotg",
> .data = dwc2_set_stm32mp15_hsotg_params },
> + { .compatible = "intel,socfpga-agilex-hsotg",
> + .data = dwc2_set_socfpga_agilex_params },
> {},
> };
> MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
