Hi,
On Thu, Nov 25, 2021 at 04:38:20PM +0200, Gil Fine wrote:
> diff --git a/drivers/thunderbolt/tb_regs.h b/drivers/thunderbolt/tb_regs.h
> index 08f1213ea565..4786e15241c8 100644
> --- a/drivers/thunderbolt/tb_regs.h
> +++ b/drivers/thunderbolt/tb_regs.h
> @@ -307,6 +307,10 @@ struct tb_regs_port_header {
> #define TMU_ADP_CS_3_UDM BIT(29)
> #define TMU_ADP_CS_6 0x06
> #define TMU_ADP_CS_6_DTS BIT(1)
> +/* Used for Titan Ridge only */
> +#define TMU_ADP_CS_6_DISABLE_TMU_OBJ_MASK GENMASK(3, 2)
> +#define TMU_ADP_CS_6_DISABLE_TMU_OBJ_CL1 BIT(2)
> +#define TMU_ADP_CS_6_DISABLE_TMU_OBJ_CL2 BIT(3)
I think these should be part of the Thunderbolt (legacy) specific
registers as below (these are not in the USB4 spec).
>
> /* Lane adapter registers */
> #define LANE_ADP_CS_0 0x00
> @@ -447,8 +451,33 @@ struct tb_regs_hop {
> } __packed;
>
> /* TMU Thunderbolt 3 registers */
> -#define TB_TIME_VSEC_3_CS_26 0x1a
> -#define TB_TIME_VSEC_3_CS_26_TD BIT(22)
> +#define TB_TIME_VSEC_3_CS_9 0x9
> +#define TB_TIME_VSEC_3_CS_9_TMU_OBJ_MASK GENMASK(17, 16)
> +#define TB_TIME_VSEC_3_CS_26 0x1a
> +#define TB_TIME_VSEC_3_CS_26_TD BIT(22)
