On Fri, 2021-08-06 at 14:43 -0600, Rob Herring wrote: > On Fri, Jul 30, 2021 at 04:49:54PM +0800, Chunfeng Yun wrote: > > There are 4 USB controllers on MT8195, the controllers (IP1~IP3, > > exclude IP0) have a wrong default SOF/ITP interval which is > > calculated from the frame counter clock 24Mhz by default, but > > in fact, the frame counter clock is 48Mhz, so we should set > > the accurate interval according to 48Mhz. Here add a new compatible > > for MT8195, it's also supported in driver. But the first controller > > (IP0) has no such issue, we prefer to use generic compatible, > > e.g. mt8192's compatible. > > That only works until you find some 8195 bug common to all > instances. It's also OK for IP0 to use mt8195's compatible, these setting value is the same as IP0's default value, use mt8192's may avoid these dummy setting. > Can't you read the clock frequency? No, it may be divided internally, not the same as the clock source. > > > > > Signed-off-by: Chunfeng Yun <chunfeng.yun@xxxxxxxxxxxx> > > --- > > Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk- > > xhci.yaml b/Documentation/devicetree/bindings/usb/mediatek,mtk- > > xhci.yaml > > index 61a0e550b5d6..753e043e5327 100644 > > --- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml > > +++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml > > @@ -31,6 +31,7 @@ properties: > > - mediatek,mt8173-xhci > > - mediatek,mt8183-xhci > > - mediatek,mt8192-xhci > > + - mediatek,mt8195-xhci > > - const: mediatek,mtk-xhci > > > > reg: > > -- > > 2.18.0 > > > >
