On Thu, Aug 05, 2021 at 06:36:17PM +0530, Sanjay R Mehta wrote:
>
>
> On 8/5/2021 6:26 PM, Mika Westerberg wrote:
> > [CAUTION: External Email]
> >
> > On Wed, Aug 04, 2021 at 06:48:45PM +0300, Mika Westerberg wrote:
> >> Hi,
> >>
> >> On Tue, Aug 03, 2021 at 07:34:54AM -0500, Sanjay R Mehta wrote:
> >>> From: Sanjay R Mehta <sanju.mehta@xxxxxxx>
> >>>
> >>> As per USB4 spec by default "Disable ISR Auto-Clear" bit is set to 0,
> >>> and the Tx/Rx ring interrupt status is needs to be cleared.
> >>>
> >>> Hence handling it by reading the "Interrupt status" register in the ISR.
> >>>
> >>> Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@xxxxxxx>
> >>> Signed-off-by: Sanjay R Mehta <sanju.mehta@xxxxxxx>
> >>> ---
> >>> drivers/thunderbolt/nhi.c | 14 ++++++++++++++
> >>> 1 file changed, 14 insertions(+)
> >>>
> >>> diff --git a/drivers/thunderbolt/nhi.c b/drivers/thunderbolt/nhi.c
> >>> index ef01aa6..7ad2202 100644
> >>> --- a/drivers/thunderbolt/nhi.c
> >>> +++ b/drivers/thunderbolt/nhi.c
> >>> @@ -373,11 +373,25 @@ void tb_ring_poll_complete(struct tb_ring *ring)
> >>> }
> >>> EXPORT_SYMBOL_GPL(tb_ring_poll_complete);
> >>>
> >>> +static void check_and_clear_intr_status(struct tb_ring *ring)
> >>> +{
> >>> + if (!(ring->nhi->pdev->vendor == PCI_VENDOR_ID_INTEL)) {
> >>> + if (ring->is_tx)
> >>> + ioread32(ring->nhi->iobase
> >>> + + REG_RING_NOTIFY_BASE);
> >>> + else
> >>> + ioread32(ring->nhi->iobase
> >>> + + REG_RING_NOTIFY_BASE
> >>> + + 4 * (ring->nhi->hop_count / 32));
> >>> + }
> >>> +}
> >>
> >> I'm now playing with this series on Intel hardware. I wanted to check
> >> from you whether the AMD controller implements the Auto-Clear feature? I
> >> mean if we always clear bit 17 of the Host Interface Control register do
> >> you still need to call the above or it is cleared automatically?
> >>
> >> I'm hoping that we could make this work on all controllers without too
> >> many special cases ;-)
> >
> > I mean if you replace patches 1 and 2 in this series with the below,
> > does it work with the AMD controller too?
> >
> Actually, it wont work on AMD controller because explicit read operation
> of interrupt status is required to clear it.
Indeed, I misunderstood the bit. Please ignore this.
