Felipe Balbi wrote:
>
> Hi,
>
> Thinh Nguyen <Thinh.Nguyen@xxxxxxxxxxxx> writes:
>> Wesley Cheng wrote:
>>> Some devices have USB compositions which may require multiple endpoints
>>> that support EP bursting. HW defined TX FIFO sizes may not always be
>>> sufficient for these compositions. By utilizing flexible TX FIFO
>>> allocation, this allows for endpoints to request the required FIFO depth to
>>> achieve higher bandwidth. With some higher bMaxBurst configurations, using
>>> a larger TX FIFO size results in better TX throughput.
>>>
>>> By introducing the check_config() callback, the resizing logic can fetch
>>> the maximum number of endpoints used in the USB composition (can contain
>>> multiple configurations), which helps ensure that the resizing logic can
>>> fulfill the configuration(s), or return an error to the gadget layer
>>> otherwise during bind time.
>>>
>>> Signed-off-by: Wesley Cheng <wcheng@xxxxxxxxxxxxxx>
>>> ---
>>> drivers/usb/dwc3/core.c | 15 +++
>>> drivers/usb/dwc3/core.h | 16 ++++
>>> drivers/usb/dwc3/ep0.c | 2 +
>>> drivers/usb/dwc3/gadget.c | 232 ++++++++++++++++++++++++++++++++++++++++++++++
>>> 4 files changed, 265 insertions(+)
>>>
<snip>
>>> +/*
>>> + * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
>>> + * @dwc: pointer to our context structure
>>> + *
>>> + * This function will a best effort FIFO allocation in order
>>> + * to improve FIFO usage and throughput, while still allowing
>>> + * us to enable as many endpoints as possible.
>>> + *
>>> + * Keep in mind that this operation will be highly dependent
>>> + * on the configured size for RAM1 - which contains TxFifo -,
>>> + * the amount of endpoints enabled on coreConsultant tool, and
>>> + * the width of the Master Bus.
>>> + *
>>> + * In general, FIFO depths are represented with the following equation:
>>> + *
>>> + * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
>>> + *
>>> + * In conjunction with dwc3_gadget_check_config(), this resizing logic will
>>> + * ensure that all endpoints will have enough internal memory for one max
>>> + * packet per endpoint.
>>> + */
>>> +static int dwc3_gadget_resize_tx_fifos(struct dwc3_ep *dep)
>>> +{
>>> + struct dwc3 *dwc = dep->dwc;
>>> + int fifo_0_start;
>>> + int ram1_depth;
>>> + int fifo_size;
>>> + int min_depth;
>>> + int num_in_ep;
>>> + int remaining;
>>> + int num_fifos = 1;
>>> + int fifo;
>>> + int tmp;
>>> +
>>> + if (!dwc->do_fifo_resize)
>>> + return 0;
>>> +
>>> + /* resize IN endpoints except ep0 */
>>> + if (!usb_endpoint_dir_in(dep->endpoint.desc) || dep->number <= 1)
>>> + return 0;
>>
>>> +
>>> + ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
>>> +
>>> + if ((dep->endpoint.maxburst > 1 &&
>>> + usb_endpoint_xfer_bulk(dep->endpoint.desc)) ||
>>> + usb_endpoint_xfer_isoc(dep->endpoint.desc))
>>> + num_fifos = 3;
>>> +
>>> + if (dep->endpoint.maxburst > 6 &&
>>> + usb_endpoint_xfer_bulk(dep->endpoint.desc) && DWC3_IP_IS(DWC31))
>>> + num_fifos = dwc->tx_fifo_resize_max_num;
>>
>> Why only bulk? Isoc should be at least equal or more than bulk.
>> Also, make this applicable to DWC_usb32 also.
>
> this should be applicable to all DWC3 versions, no? dwc3, 31 and 32.
>
Yes.
BR,
Thinh
