Hi, On Tue, May 25, 2021 at 12:29:01PM +0100, Andre Przywara wrote: > On Mon, 24 May 2021 13:59:46 +0200 > Maxime Ripard <maxime@xxxxxxxxxx> wrote: > > Hi Maxime, > > > On Wed, May 19, 2021 at 11:41:47AM +0100, Andre Przywara wrote: > > > At least the Allwinner H616 SoC requires a weird quirk to make most > > > USB PHYs work: Only port2 works out of the box, but all other ports > > > need some help from this port2 to work correctly: The CLK_BUS_PHY2 and > > > RST_USB_PHY2 clock and reset need to be enabled, and the SIDDQ bit in > > > the PMU PHY control register needs to be cleared. For this register to > > > be accessible, CLK_BUS_ECHI2 needs to be ungated. Don't ask .... > > > > > > Instead of disguising this as some generic feature, do exactly that > > > in our PHY init: > > > If the quirk bit is set, and we initialise a PHY other than PHY2, ungate > > > this one special clock, and clear the SIDDQ bit. We can pull in the > > > other required clocks via the DT. > > > > > > Signed-off-by: Andre Przywara <andre.przywara@xxxxxxx> > > > > What is this SIDDQ bit doing exactly? > > I probably know as much as you do, but as Jernej pointed out, in some > Rockchip code it's indeed documented as some analogue PHY supply switch: > ($ git grep -i siddq drivers/phy/rockchip) > > In fact we had this pin/bit for ages, it was just hidden as BIT(1) in > our infamous PMU_UNK1 register. Patch 10/17 drags that into the light. Ok > > I guess we could also expose this using a power-domain if it's relevant? > > Mmmh, interesting idea. So are you thinking about registering a genpd > provider in sun4i_usb_phy_probe(), then having a power-domains property > in the ehci/ohci nodes, pointing to the PHY node? And if yes, should > the provider be a subnode of the USB PHY node, with a separate > compatible? That sounds a bit more involved, but would have the > advantage of allowing us to specify the resets and clocks from PHY2 > there, and would look a bit cleaner than hacking them into the > other EHCI/OHCI nodes. I'm not sure we need a separate device node, we could just register the phy driver as a genpd provider, and then with an arg (so with of_genpd_add_provider_onecell?) the index of the USB controller we want to power up. > I would not touch the existing SoCs (even though it seems to apply to > them as well, just not in the exact same way), but I can give it a > try for the H616. It seems like the other SIDDQ bits (in the other > PHYs) are still needed for operation, but the PD provide could actually > take care of this as well. > > Does that make sense or is this a bit over the top for just clearing an > extra bit? Using what I described above should be fairly simple, so if we can fit in an available and relevant abstraction, yeah, I guess :) Maxime
Attachment:
signature.asc
Description: PGP signature
