HI,
Michael Grzeschik <mgr@xxxxxxxxxxxxxx> writes:
<big snip>
>>>>> kworker/u5:1-74 [000] d..2 56.807831: dwc3_ep_queue: ep2in: req 00000000f5394c5d length 0/3072 zsi ==> -115
>>>>> kworker/u5:1-74 [000] d..2 56.807857: dwc3_ep_queue: ep2in: req 00000000ef95b55c length 0/3072 zsi ==> -115
>>>>> kworker/u5:1-74 [000] d..2 56.807883: dwc3_ep_queue: ep2in: req 00000000d36cf0cc length 0/3072 zsi ==> -115
>>>>> kworker/u5:1-74 [000] d..2 56.807908: dwc3_ep_queue: ep2in: req 00000000c5f1bd4b length 0/3072 zsi ==> -115
>>>>> kworker/u5:1-74 [000] d..2 56.807934: dwc3_ep_queue: ep2in: req 00000000b7180b2d length 0/3072 zsi ==> -115
>>>>> kworker/u5:1-74 [000] d..2 56.807960: dwc3_ep_queue: ep2in: req 000000005d629ded length 0/3072 zsi ==> -115
>>>>> kworker/u5:1-74 [000] d..2 56.807985: dwc3_ep_queue: ep2in: req 0000000062e02cc0 length 0/3072 zsi ==> -115
>>>>> kworker/u5:1-74 [000] d..2 56.808011: dwc3_ep_queue: ep2in: req 000000001d2ec1c0 length 0/3072 zsi ==> -115
>>>>> kworker/u5:1-74 [000] d..2 56.808038: dwc3_ep_queue: ep2in: req 0000000018ba3d29 length 0/3072 zsi ==> -115
>>>>> kworker/u5:1-74 [000] d..2 56.808063: dwc3_ep_queue: ep2in: req 000000000be47fc7 length 0/3072 zsi ==> -115
>>>>> kworker/u5:1-74 [000] d..2 56.808089: dwc3_ep_queue: ep2in: req 00000000caba09e2 length 0/3072 zsi ==> -115
>>>>> kworker/u5:1-74 [000] d..2 56.808115: dwc3_ep_queue: ep2in: req 00000000cb0191c4 length 0/3072 zsi ==> -115
>>>>> kworker/u5:1-74 [000] d..2 56.808140: dwc3_ep_queue: ep2in: req 000000005255f606 length 0/3072 zsi ==> -115
>>>>> irq/51-dwc3-239 [000] d..1 56.808240: dwc3_event: event (d1d0408a): ep2in: Transfer In Progress [0000d1d0] (sIm)
>>>>
>>>>eventually we get Transfer In Progress for the first TRB...
>>>>
>>>>> irq/51-dwc3-239 [000] d..1 56.808246: dwc3_complete_trb: ep2in: trb 000000007ebd2707 (E2:D1) buf 000000000c623058 size 1x 0 ctrl 34740464:0000d1d0 (hlCs:Sc:isoc-first)
>>>>> irq/51-dwc3-239 [000] d..1 56.808250: dwc3_complete_trb: ep2in: trb 0000000093bb2bc4 (E2:D2) buf 000000000e200000 size 1x 0 ctrl 34740c70:0000d1d0 (hlcs:SC:isoc)
>>>>> irq/51-dwc3-239 [000] d..1 56.808256: dwc3_gadget_giveback: ep2in: req 00000000823b0b62 length 3072/3072 zsI ==> 0
>>>>
>>>>complete and give it back.
>>>>
>>>>> irq/51-dwc3-239 [000] d..1 56.808305: dwc3_prepare_trb: ep2in: trb 000000004af35733 (E3:D2) buf 000000000c623088 size 1x 2 ctrl 00000465:00000000 (HlCs:Sc:isoc-first)
>>>>> irq/51-dwc3-239 [000] d..1 56.808309: dwc3_prepare_trb: ep2in: trb 00000000a11671a8 (E4:D2) buf 000000000e200bfe size 1x 3070 ctrl 00000471:00000000 (Hlcs:Sc:isoc)
>>>>
>>>>prepare the next
>>>>
>>>>> irq/51-dwc3-239 [000] d..1 56.808320: dwc3_gadget_ep_cmd: ep2in: cmd 'Update Transfer' [50407] params 00000000 00000000 00000000 --> status: Successful
>>>>
>>>>kick it by telling the HW about it. I don't see any failures here,
>>>>although there may be situations where we could add more data to the
>>>>controller's cache early on.
>>>
>>> I back that Idea of adding more data to the controllers cache early.
>>
>>right, and that's where things get complicated because we don't have
>>enough information from ISOC endpoints to schedule transfers to correct
>>microframes. We're missing two bits which are only shared with us by the
>>HW during XferInProgress and XferNotReady (IIRC).
>
> No! For Isoc we never miss these bits. I understand that driver part
> already good enough.
>
> Because once the transfer is started every ep_queue (respectively every
> update transfer) will only add trbs to the running transfer. These
> updates have no timestamp information. Just look into the update
> transfer command.
right, the details of that are fuzzy for me since I haven't directly
touched this part of the driver in quite a while but IIRC, Update
Transfer should be used only to add transfer to the current *service
interval*; meaning that if you continuously Update Transfer, you will
run into bus expiry.
Thinh, any chance you can shed some light here?
> When the update transfer is called not later than the last trb from the
> current transfer was handled in hardware, then everything will run
> smooth. In the other case, when the update transfer was called after the
Sure, but this poses another requirement on the Gadget API that
transfers must be ready in a timely fashion. Currently, there's no way
for gadget driver to guarantee this requirement, specially since for
video frames processing is off-loaded to a userspace component. The
latency involved here may be quite large.
I have memories that what you say is exactly what we used to do but it
turned out that it was far too easy to get out of sync between dwc3,
g_webcam and the userspace component.
> trbs from the current transfer did run out we will receive a missed
> interrupt for that new udpated trb and the driver needs to call end
> transfer so a new one is started.
True, that's not handled as of yet, IIRC. We return -EXDEV to the gadget
driver but don't really issue End Transfer
(/me checks gadget.c)
Nope, scratch that, we _do_ issue End Transfer, so something like this
*could* work. I'm still worried about the PENDING_REQUEST flag never
being cleared, though.
>>> The second one you see is already way to late for an update. It comes
>>> back as an Missed Interrupt as the Update was to late for the transfer.
>>>
>>> "irq/51-dwc3-239 [000] d..1 56.808460: dwc3_event: event (d1d1808a): ep2in: Transfer In Progress [0000d1d1] (siM)"
>>>
>>> After the missed transfer the last transfer will be ended and another transfer is prepared.
>>>
>>> "irq/51-dwc3-239 [000] d..1 56.815974: dwc3_event: event (d20e10ca): ep2in: Transfer Not Ready [0000d20e] (Not Active)"
>>>
>>> But after that and an successfull next start transfer no further completion interrupts will
>>> show up. That seems broken.
>>
>>oh, that's messed up. We should get XferInProgress.
>
> Should we? Look into the comment in transfer_not_ready call. So this in
> our case is the caller of __dwc3_gadget_start_isoc -> dwc3_prepare_trbs -> kick_transfer
> for the one next trb in the pending list.
>
> 3047 static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep,
> 3048 const struct dwc3_event_depevt *event)
> 3049 {
> 3050 dwc3_gadget_endpoint_frame_from_event(dep, event);
> 3051
> 3052 /*
> 3053 * The XferNotReady event is generated only once before the endpoint
> 3054 * starts. It will be generated again when END_TRANSFER command is
> 3055 * issued. For some controller versions, the XferNotReady event may be
> 3056 * generated while the END_TRANSFER command is still in process. Ignore
> 3057 * it and wait for the next XferNotReady event after the command is
> 3058 * completed.
> 3059 */
> 3060 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
> 3061 return;
> 3062
> 3063 (void) __dwc3_gadget_start_isoc(dep);
> 3064 }
that came from commit 36f05d36b03523da906cf2ae70ec31af6f57e94c. I don't
think the intention was for that to apply in this particular case. Thinh?
>>> "irq/51-dwc3-239 [000] d..1 56.815996: dwc3_gadget_ep_cmd: ep2in: cmd 'Start Transfer' [d2120406] params 00000000 0a6ab040 00000000 --> status: Successful"
>>>
>>> It looks like the underlying issue I could avoid with my patches. However not
>>> updating the transfer and running into missed interrupts is another issue
>>> that needs to be solved.
>>
>>my concern is that you may be regressing other parts of the driver :-)
>
> We should obviously check for that. But for isoc I did not see any problem.
Did you test both audio and video gadgets? HS and SS?
>>How about we look into the fact that PENDING_REQUEST is never cleared
>>first?
>
> We can do that as well. But my head is issueing the pre-starting task now! :)
heh :-) As I mentioned, I fear we may end up opening a can of worms if
we change this part without guaranteeing that all the driver flags are
in the correct state first.
>>>>I remember dealing with a bunch of Bus Expiry errors in the past and the
>>>>problem was because we couldn't maintain proper alignment with the
>>>>microframe number because HW only gives us 14 out of the 16 bits of the
>>>>microframe number, the only workaround was to waiting for
>>>>XferInProgress/XferNotReady to get that number.
>>>
>>> I think the bus expiry or microframe handling is not a problem here.
>>
>>Not in this case because we're never pre-starting transfers. What you
>>suggest will pre-start transfers and we will have regressions.
>
> I did that, and did never see any regressions, as I explained above. Otherwise
> I would have checked for another solution, than my initial two patches.
So you tested on your usecase, with one platform. We would need more
people testing this if we want any chance of avoiding regressions, and I
still think fixing the bad flags is more important first because that
flag is used exactly to make decisions regarding Isochronous transfers.
--
balbi
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