On Wed, Mar 24, 2021 at 08:41:09AM +0100, Mauro Carvalho Chehab wrote:
> There's nothing special on this device: it has just one port.
>
> The only difference is that it uses a different register set.
Not quite true. First, it uses 12-bit registers, which the driver isn't
updated for. Similarly, it used 12-bit register *addresses* which
likewise the driver isn't updated for and the upper bits are simply
discarded.
This device also doesn't support CS5 and CS6 which would need to be
handled.
>
> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@xxxxxxxxxx>
> ---
> drivers/usb/serial/xr_serial.c | 30 ++++++++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/drivers/usb/serial/xr_serial.c b/drivers/usb/serial/xr_serial.c
> index 058624d15505..b1044dd3e994 100644
> --- a/drivers/usb/serial/xr_serial.c
> +++ b/drivers/usb/serial/xr_serial.c
> @@ -99,6 +99,7 @@ struct xr_txrx_clk_mask {
> #define VIA_CDC_REGISTER -1
>
> enum xr_model {
> + XR21B1411,
> XR21V141X,
> XR21B142X,
> MAX_XR_MODELS
> @@ -132,6 +133,30 @@ enum xr_hal_type {
> };
>
> static const int xr_hal_table[MAX_XR_MODELS][MAX_XR_HAL_TYPE] = {
> + [XR21B1411] = {
> + [REG_ENABLE] = 0xc00,
> + [REG_FORMAT] = VIA_CDC_REGISTER,
> + [REG_FLOW_CTRL] = 0xc06,
> + [REG_XON_CHAR] = 0xc07,
> + [REG_XOFF_CHAR] = 0xc08,
> + [REG_TX_BREAK] = 0xc0a,
> + [REG_RS485_DELAY] = 0xc0b,
> + [REG_GPIO_MODE] = 0xc0c,
> + [REG_GPIO_DIR] = 0xc0d,
> + [REG_GPIO_SET] = 0xc0e,
> + [REG_GPIO_CLR] = 0xc0f,
> + [REG_GPIO_STATUS] = 0xc10,
> + [REG_GPIO_INT_MASK] = 0xc11,
> + [REG_CUSTOMIZED_INT] = 0xc12,
> + [REG_GPIO_PULL_UP_ENABLE] = 0xc14,
> + [REG_GPIO_PULL_DOWN_ENABLE] = 0xc15,
> + [REG_LOOPBACK] = 0xc16,
> + [REG_LOW_LATENCY] = 0xcc2,
> + [REG_CUSTOM_DRIVER] = 0x20d,
> +
> + [REQ_SET] = 0,
> + [REQ_GET] = 1,
> + },
> [XR21V141X] = {
> [REG_ENABLE] = 0x03,
> [REG_FORMAT] = 0x0b,
Johan
