Hi Peter, > >Hi Pawel, > >From the code of this file, it seems the controller driver is running at >PC side, but the hardware controller is at verification board, the two sides >are connected by PCIe. Am I right? > >If I am right, the memory (eg, the TRB ring address and data buffer) the hardware >try to visit is at PC side, but how controller visits PC memory since the TRB ring >address is allocated dynamically by controller device driver running at >PC? How the local bus arbiter knows it is PCIe address at verification board? >Besides, could the upstream code run this IP verification solution through PCIe >without changing any code? Yes, the two sides, verification board and PC are connected by PCIe cable connected by using special PCIe adapters. The PC sees FPGA board as the part of PC hardware. It's work in the same way as standard XHCI controller based on PCIe. > >Thanks. > >-- > >Thanks, >Peter Chen Regards, Pawel Laszczak
