On 22.10.2020 6.01, Peter Chen wrote:
> The Cadence xHCI host has the same issue with Intel's,
> it is triggered by reboot stress test.
>
> Cc: Pawel Laszczak <pawell@xxxxxxxxxxx>
> Cc: Roger Quadros <rogerq@xxxxxx>
> Signed-off-by: Peter Chen <peter.chen@xxxxxxx>
> ---
> drivers/usb/host/xhci.c | 2 +-
> drivers/usb/host/xhci.h | 1 +
> 2 files changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
> index 482fe8c5e3b4..fc72a03dc27f 100644
> --- a/drivers/usb/host/xhci.c
> +++ b/drivers/usb/host/xhci.c
> @@ -193,7 +193,7 @@ int xhci_reset(struct xhci_hcd *xhci)
> * Without this delay, the subsequent HC register access,
> * may result in a system hang very rarely.
> */
> - if (xhci->quirks & XHCI_INTEL_HOST)
> + if (xhci->quirks & (XHCI_INTEL_HOST | XHCI_CDNS_HOST))
> udelay(1000);
>
> ret = xhci_handshake(&xhci->op_regs->command,
> diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
> index 8be88379c0fb..4b7275c73ea5 100644
> --- a/drivers/usb/host/xhci.h
> +++ b/drivers/usb/host/xhci.h
> @@ -1877,6 +1877,7 @@ struct xhci_hcd {
> #define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35)
> #define XHCI_RENESAS_FW_QUIRK BIT_ULL(36)
> #define XHCI_SKIP_PHY_INIT BIT_ULL(37)
> +#define XHCI_CDNS_HOST BIT_ULL(38)
>
> unsigned int num_active_eps;
> unsigned int limit_active_eps;
>
Is the XHCI_CDNS_HOST quirk bit set in some other patchseries?
-Mathias
