Re: [PATCH v3 02/15] clk: tegra: Don't enable PLLE HW sequencer at init

[Thierry Reding <thierry.reding@xxxxxxxxx>]

On Wed, Sep 09, 2020 at 04:10:28PM +0800, JC Kuo wrote:
> PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware
> power sequencers' output to enable/disable PLLE. PLLE hardware power
> sequencer has to be enabled only after PEX/SATA UPHY PLL's sequencers
> are enabled.
> 
> Signed-off-by: JC Kuo <jckuo@xxxxxxxxxx>
> ---
> v3:
>    no change
> 
>  drivers/clk/tegra/clk-pll.c | 12 ------------
>  1 file changed, 12 deletions(-)

Acked-by: Thierry Reding <treding@xxxxxxxxxx>

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