Hi Mauro,
Mauro Carvalho Chehab <mchehab+huawei@xxxxxxxxxx> writes:
> Hi Felipe/Greg,
>
> What's the status of this patch?
to be frank, I don't think I have this in my inbox anymore.
> I tested here, together with the Hikey 970 phy RFC patches I sent
> last week.
>
> Without this patch, the USB HID driver receives -EPROTO from
> submitted URBs, causing it to enter into an endless reset cycle
> on every 500 ms, at the hid_io_error() logic.
> Tested-by: Mauro Carvalho Chehab <mchehab+huawei@xxxxxxxxxx>
>
> If you prefer, I can re-submit this one with my SOB.
Please do, but since you're changing device tree, I need Rob's acked-by.
> Thanks,
> Mauro
>
> Em Sat, 20 Apr 2019 14:40:10 +0800
> Yu Chen <chenyu56@xxxxxxxxxx> escreveu:
>
>> SPLIT_BOUNDARY_DISABLE should be set for DesignWare USB3 DRD Core
>> of Hisilicon Kirin Soc when dwc3 core act as host.
is this Kirin-specific or is this something that we should do a revision
check? Why does it affect only Hikey kirin? What's the dwc3 revision on
that SoC (grep SNPSID /sys/kernel/debugfs/*dwc3/regdump)?
>> @@ -1825,10 +1834,27 @@ static int dwc3_resume(struct device *dev)
>>
>> return 0;
>> }
>> +
>> +static void dwc3_complete(struct device *dev)
>> +{
>> + struct dwc3 *dwc = dev_get_drvdata(dev);
>> + u32 reg;
>> +
>> + if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
>> + dwc->dis_split_quirk) {
>> + dev_dbg(dwc->dev, "set DWC3_GUCTL3_SPLITDISABLE\n");
no more dev_dbg() should be added. This driver relies exclusively on
tracepoints for debugging.
>> + reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
>> + reg |= DWC3_GUCTL3_SPLITDISABLE;
>> + dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
>> + }
>> +}
>> +#else
>> +#define dwc3_complete NULL
>> #endif /* CONFIG_PM_SLEEP */
>>
>> static const struct dev_pm_ops dwc3_dev_pm_ops = {
>> SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
>> + .complete = dwc3_complete,
why is this done on complete? Why can't it be done at the end of
dwc3_resume()?
--
balbi
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