From: Jeremy Kerr <jk@xxxxxxxxxx>
Date: Tue, 16 Jun 2020 17:08:23 +0800
>> Because that code in this loop makes the same calculations:
>>
>> ax_skb = skb_clone(skb, GFP_ATOMIC);
>> if (ax_skb) {
>> ax_skb->len = pkt_len;
>> ax_skb->data = skb->data + 2;
>> skb_set_tail_pointer(ax_skb, pkt_len);
>> ax_skb->truesize = pkt_len + sizeof(struct sk_buff);
>> ax88179_rx_checksum(ax_skb, pkt_hdr);
>> usbnet_skb_return(dev, ax_skb);
>>
>> So if your change is right, it should be applied to this code block
>> as well.
>
> Yep, my patch changes that block too (or did I miss something?)
Nope, you didn't miss anything. I missed that completely.
>> And do we know that it's two extra tail bytes always? Or some kind
>> of alignment padding the chip performs for every sub-packet?
>
> I've assumed it's a constant two bytes of prefix padding, as that's all
> I've seen. But it would be great to have more detail from ASIX if
> possible.
I'll wait a bit for the ASIX folks to comment.
It seems logical to me that what the chip does is align up the total
sub-packet length to a multiple of 4 or larger, and then add those two
prefix padding bytes. Otherwise the prefix padding won't necessarily
and reliably align the IP header after the link level header.
Thanks.
