The Synopsys xHC has an internal TRB cache of size TRB_CACHE_SIZE for each endpoint. The default value for TRB_CACHE_SIZE is 16 for SS and 8 for HS. The controller loads and updates the TRB cache from the transfer ring in system memory whenever the driver issues a start transfer or update transfer command. For chained TRBs, the Synopsys xHC requires that the total amount of bytes for all TRBs loaded in the TRB cache be greater than or equal to 1 MPS. Or the chain ends within the TRB cache (with a last TRB). If this requirement is not met, the controller will not be able to send or receive a packet and it will hang causing a driver timeout and error. This patch set adds logic to the XHCI driver to detect and prevent this from happening along with the quirk to enable this logic for Synopsys HAPS platform. Based on Mathias's feedback on previous implementation where consolidation was done in TRB cache, with this patch series the implementation is done during mapping of the URB by consolidating the SG list into a temporary buffer if the SG list buffer sizes within TRB_CACHE_SIZE is less than MPS. Changes since v1: - Comments from Greg are addressed on [PATCH 4/4] and [PATCH 1/4] - Renamed the property and quirk as in other patches based on [PATCH 1/4] Tejas Joglekar (4): dt-bindings: usb: Add documentation for SG trb cache size quirk usb: xhci: Set quirk for XHCI_SG_TRB_CACHE_SIZE_QUIRK usb: dwc3: Add device property sgl-trb-cache-size-quirk usb: xhci: Use temporary buffer to consolidate SG Documentation/devicetree/bindings/usb/dwc3.txt | 4 + Documentation/devicetree/bindings/usb/usb-xhci.txt | 3 + drivers/usb/dwc3/core.c | 2 + drivers/usb/dwc3/core.h | 2 + drivers/usb/dwc3/dwc3-haps.c | 1 + drivers/usb/dwc3/host.c | 6 +- drivers/usb/host/xhci-pci.c | 3 + drivers/usb/host/xhci-plat.c | 4 + drivers/usb/host/xhci-ring.c | 2 +- drivers/usb/host/xhci.c | 125 +++++++++++++++++++++ drivers/usb/host/xhci.h | 5 + 11 files changed, 155 insertions(+), 2 deletions(-) -- 2.11.0
