On Sat, 29 Feb 2020 at 18:33, Antti Seppälä <a.seppala@xxxxxxxxx> wrote:
>
> On Sat, 29 Feb 2020 at 17:25, Guenter Roeck <linux@xxxxxxxxxxxx> wrote:
> >
> > Sigh. It would have been too simple. Too bad I can't test myself.
> > I'd like to know if this is because URB_NO_TRANSFER_DMA_MAP is set on a
> > transfer, or because the beginning of the buffer indeed needs to be aligned
> > to the DMA cache line size on that system. In the latter case, the question
> > is why the alignment to DWC2_USB_DMA_ALIGN (=4) works. In the former case,
> > question would be why the realignment does any good in the first place.
> >
> > Any chance you can add some test code to help figuring out what exactly
> > goes wrong ?
> >
>
> Sure, I can try to help. Just let me know what code you would like to
> insert and where and I'll see what I can do.
>
So I did some further research on this and it turns out that:
- URB_NO_TRANSFER_DMA_MAP is not set on the offending transfers so
the issue really is buffer alignment
- DWC2_USB_DMA_ALIGN=4 "works" because in my limited testcase (usb
4g-dongle utilized via qmi-wwan) all transfers are unaligned. That is,
every urb->transfer_buffer is misaligned by 2 bytes == unaligned
- I can fix both issues and thus make the patch work on MIPS by
modifying it like this:
-#define DWC2_USB_DMA_ALIGN 4
+#define DWC2_USB_DMA_ALIGN dma_get_cache_alignment()
struct dma_aligned_buffer {
void *old_xfer_buffer;
- u8 data[0];
+ u8 data[0] ____cacheline_aligned;
};
--
Antti
