Hi Hanjie,
overall this looks good to me and I have one question
On Fri, Dec 27, 2019 at 7:37 AM Hanjie Lin <hanjie.lin@xxxxxxxxxxx> wrote:
[...]
> + if (priv->soc_id == MESON_SOC_A1)
> + value |= PHY_CTRL_R18_MPLL_DCO_CLK_SEL;
...here we have some CLK_SEL bit
[...]
> - priv->clk = devm_clk_get(dev, "xtal");
> - if (IS_ERR(priv->clk))
> - return PTR_ERR(priv->clk);
> + if (priv->soc_id == MESON_SOC_G12A) {
> + priv->clk = devm_clk_get(dev, "xtal");
> + if (IS_ERR(priv->clk))
> + return PTR_ERR(priv->clk);
> + }
but here we don't need any parent/input clock?
does this mean that the USB2 PHY on the A1 SoC doesn't have any clock
inputs? how does it generate the correct clock for itself then?
Martin
