[PATCH v2 2/6] dt-bindings: usb: dwc3: Add the Amlogic A1 Family DWC3 Glue Bindings

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The Amlogic A1 SoC Family embeds 1 USB Controllers:
 - a DWC3 IP configured as Host for USB2 and USB3

A glue connects the controllers to the USB2 PHY of A1 SoC.

Signed-off-by: Hanjie Lin <hanjie.lin@xxxxxxxxxxx>
Signed-off-by: Yue Wang <yue.wang@xxxxxxxxxxx>
---
 .../bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml  | 32 ++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml b/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml
index 4efb77b..9740027 100644
--- a/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml
+++ b/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml
@@ -9,6 +9,8 @@ title: Amlogic Meson G12A DWC3 USB SoC Controller Glue
 
 maintainers:
   - Neil Armstrong <narmstrong@xxxxxxxxxxxx>
+  - Hanjie Lin <hanjie.lin@xxxxxxxxxxx>
+  - Yue Wang <yue.wang@xxxxxxxxxxx>
 
 description: |
   The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3
@@ -22,10 +24,14 @@ description: |
   The DWC3 Glue controls the PHY routing and power, an interrupt line is
   connected to the Glue to serve as OTG ID change detection.
 
+  The Amlogic A1 embeds a DWC3 USB IP Core configured for USB2 in
+  host-only mode.
+
 properties:
   compatible:
     enum:
       - amlogic,meson-g12a-usb-ctrl
+      - amlogic,meson-a1-usb-ctrl
 
   ranges: true
 
@@ -124,4 +130,30 @@ examples:
               snps,quirk-frame-length-adjustment;
           };
     };
+  - |
+    usb: usb@ffe09000 {
+          status = "okay";
+          compatible = "amlogic,meson-a1-usb-ctrl";
+          reg = <0x0 0xffe09000 0x0 0xa0>;
+          #address-cells = <2>;
+          #size-cells = <2>;
+          ranges;
 
+          clocks = <&clkc_periphs CLKID_USB_CTRL>,
+           <&clkc_periphs CLKID_USB_BUS>,
+           <&clkc_periphs CLKID_XTAL_USB_PHY>,
+           <&clkc_periphs CLKID_XTAL_USB_CTRL>;
+          clock-names = "usb_ctrl", "usb_bus", "xtal_usb_phy", "xtal_usb_ctrl";
+          resets = <&reset RESET_USBCTRL>;
+          phys = <&usb2_phy0>;
+          phy-names = "usb2-phy0";
+
+          dwc3: usb@ff400000 {
+                  compatible = "snps,dwc3";
+                  reg = <0x0 0xff400000 0x0 0x100000>;
+                  interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+                  dr_mode = "host";
+                  snps,dis_u2_susphy_quirk;
+                  snps,quirk-frame-length-adjustment = <0x20>;
+          };
+  };
-- 
2.7.4




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