DWC_usb32 has an enhancement that allows the controller to cache multiple TRBs for non-control endpoints. Introduce a new property to DWC3 to set the maximum number of TRBs to cache in advance. The property can be set from 1 to DWC_USB32_CACHE_TRBS_PER_TRANSFER (CoreConsultant value). By default, the number of cache TRB is DWC_USB32_CACHE_TRBS_PER_TRANSFER. Signed-off-by: Thinh Nguyen <thinhn@xxxxxxxxxxxx> --- Documentation/devicetree/bindings/usb/dwc3.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt index 7da1c4e7d380..ff35fa6de2eb 100644 --- a/Documentation/devicetree/bindings/usb/dwc3.txt +++ b/Documentation/devicetree/bindings/usb/dwc3.txt @@ -105,6 +105,9 @@ Optional properties: this and tx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31 programming guide section 1.2.3) to enable periodic ESS TX threshold. + - snps,num-trb-prefetch: max value to do TRBs cache for DWC_usb32. The value + can be from 1 to DWC_USB32_CACHE_TRBS_PER_TRANSFER. + Default value is DWC_USB32_CACHE_TRBS_PER_TRANSFER. - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to be reallocated. - snps,incr-burst-type-adjustment: Value for INCR burst type of GSBUSCFG0 -- 2.11.0
