Hi Bjorn, Any further ideas here? Do we go ahead with the quirk or try to find a more generic approach? On Mon, Oct 28, 2019 at 2:32 PM Daniel Drake <drake@xxxxxxxxxxxx> wrote: > It looks like we can detect that the reset has failed (or more > precisely, not quite completed) by reading PCI_COMMAND (value not yet > 0) or PCI_PM_CTRL (doesn't yet indicate D0 state, we already log a > warning for this case). > > From that angle, another workaround possibility is to catch that case > and then retry the PCI_PM_CTRL write and delay once more. Thanks Daniel
