Hi, Sorry for the delay. I was on vacation last week. On Tue, Oct 15, 2019 at 01:31:32PM +0800, Daniel Drake wrote: > On Mon, Oct 14, 2019 at 11:43 PM Bjorn Helgaas <helgaas@xxxxxxxxxx> wrote: > > Can you tell if this is because the Ryzen7 XHCI controller is out of > > spec, or is the Linux PCI core missing some delay? If the latter, > > fixing the core might fix other devices as well. > > > > Mika has this patch: > > https://lore.kernel.org/r/20190821124519.71594-1-mika.westerberg@xxxxxxxxxxxxxxx > > for similar issues, but I think that patch fixes D3cold->D0 > > transitions, and your patch appears to be concerned with D3hot->D0 > > transitions. > > It's actually coming out of D3cold here, however what happens right > before this is that __pci_start_power_transition() calls > pci_platform_power_transition(D0) to leave D3cold state, then > pci_update_current_state() reads PMCSR and updates dev->current_state > to D3hot. > > The 20ms delay for these XHCI controllers is needed precisely at this > point - after writing PMCSR to move to D0, and before reading it back > to check the result. > I tried moving the delay immediately before writing PMCSR, but that > doesn't work. Based on that, it seems like it's just a little out of > spec. > > With Mika's patch, pcie_wait_downstream_accessible() is called for > these devices after the state transition has already failed. It also > doesn't do any delaying at that point because pci_pcie_type(pdev) == > 0. Just to be sure, did you try the patch or just looked at it? Because what the patch does is that it does the delay when the downstream/root port is resumed, not the xHCI itself.
