Re: DMA Cache problem for control transfers

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2009/5/31 Martin Fuzzey <mfuzzey@xxxxxxxxx>:
> Hi,
> I've found out why test13 is failing for me on i.MX21. I don't think
> it's related to my HCD but I'm not sure if it's an ARM or USB problem :
>
> When the problem occurs I noticed that both the setup phase buffer and
> the data phase buffer are in the same 32 byte block.
> As dma_get_cache_alignment() returns 32 on this platform I believe they
> share a cache line.
>
> So this means that when performing the GET_STATUS request the usb core
> is calling:
>    dma_map_single(DMA_TO_DEVICE) for the 8 byte setup buffer
>    dma_map_single(DMA_FROM_DEVICE) for the 2 byte data buffer
>
> and that when the problem occurs both buffers are in the same cache line..
> This causes the data seen in main memory for the data buffer to be
> incorrect.
>
> Attached is a patch to demonstrate the problem.
> It adds a new usbtest case (#20) which uses the -s parameter to mean
> alignment.
> It then just does GET_STATUS requests in a loop (without halts or
> anything else).
>
> So
> ./testusb -c 1000 -s 32 -a -t 20   never fails
> whereas
> ./testusb -c 1000 -s 16 -a -t 20   fails within a few iterations
>
> I'm not sure how to fix this - normally the setup buffer and data
> buffers are obtained from separate kmallocs - I was just unlucky to get
> nearby addresses.

No, it is nothing to do with USB, it is a rule that buffer allocated
by kmalloc() is
cache-line aligned.

Thanks.

-- 
Lei Ming
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