Hello, On Mon, Jun 24, 2019 at 09:15:24AM +0300, Mathias Nyman wrote: > On 19.6.2019 22.03, Rob Weber wrote: > > I am working on running our custom USB dual-role product through some > > compliance testing. It seems that the SoC and host controller are > > not responding to the LFPS signaling and timeout that is supposed to > > automatically begin the compliance test sequence. > > > > I'm currently running a 4.9.115 kernel, and I'm afraid I might be > > missing some critical patches for compliance test support. I noticed > > these two patches came up in a google search: > > > > https://patchwork.kernel.org/patch/10415345/ > > https://www.spinics.net/lists/linux-usb/msg160002.html > > > > Besides these patches, is there anything else that comes to mind that I > > might need to do to start compliance testing? I'm about to build a more > > recent kernel to see if that improves my situation as well. > > If xHC hw has a "Compliance Transition Capability" (CTC) bit set in the > HCCPARAMS2 register then ports won't go to compliance unless software > specifically allows it. > > see xhci spec section 4.19.1.2.4.1 for more details. > > Compliance can be allowed either with a SetPortFeature(PORT_LINK_STATE) request, > or via debugfs. > > To allow compliance using debugfs, first check port is in disabled state: > > # cat /sys/kernel/debug/usb/xhci/0000:00:15.0/ports/port01/portsc > Powered Not-connected Disabled Link:RxDetect PortSpeed:0 Change: Wake: > > enable compliance by writing "compliance" to the port: > # echo compliance > /sys/kernel/debug/usb/xhci/0000:00:15.0/ports/port01/portsc > > This needs to be done for that specific port, and after every port warm reset. > > After 1st LFPS timeout the port should go to compliance, can be read from portsc > > Also make sure you don't have XHCI_COMP_MODE_QUIRK or XHCI_MISSING_CAS quirks set, > these try to recover ports that accidentally enter compliance mode in normal use. Thanks for the tip! I will try this approach with a newer kernel soon. I learned that the port enters compliance mode after the 1st LFPS polling timeout last week after watching the port become "disabled" after the first connection. We're currently doing a full power cycle to correct this state, but unbinding and re-binding the pci device with the xhci_hcd driver has also been successful at resetting the xHC. The portsc register and warm_reset file will help improve our workflow for compliance testing. > > Just for reference, our product uses an intel atom z8550 SoC that uses > > an xHCI host controller and a dwc3 device controller. Our platform also > > uses a USB 3.0 redriver. The datasheet for this redriver (tusb542) > > indicates that it's internal LFPS controller supports full USB 3.0 > > compliance requirements. > > > > z8550 is Cherry Trail? I unfortunately don't have those around anymore. Yeah, they are increasingly hard to come by. But so far your description aligns with our findings and research about the xHCI implementation in this SoC. Thanks for your help! Cheers, Rob Weber
