-------------- Original message from Alan Stern <stern@xxxxxxxxxxxxxxxxxxx>: --------------
> On Fri, 22 May 2009, Dwayne Fontenot wrote:
>
> > > You should try changing your driver so that it delays by one
> > > millisecond after submitting each of the initial interrupt URBs. Then
> > > different URBs will be processed during different frames and the queue
> > > depths will never get very big. The NEC controller might be able to
> > > handle this with no problem.
> > >
> > > Alan Stern
> >
> > I configured CONFIG_PRINTK_TIME=y and ran the test again.
> > The interrupt URB submissions look like this:
> >
> > [ 951.701316] usb 4-4.4.2: submitted intr urb for ru100
> > [ 951.702951] usb 4-4.4.3: submitted intr urb for ru101
> > [ 951.703770] usb 4-4.4.5: submitted intr urb for ru102
> ...
>
> > The initial interrupt URB submissions are in the probe routine of the RU
> driver.
> > It appears that they are already staggered over approx. 64 mS (?).
> >
> > The periodic schedule for the above looks like this (first six entries are the
> hubs):
> >
> > size = 256
> > 255: qh256-0001/f68e5100 (h2 ep1in [1/0] q1 p1) qh256-0001/f68e5500 (h9
> ep1in [1/0] q1 p1) qh256-0001/f68e5600 (h10 ep1in [1/0] q1 p1)
> qh256-0001/f68e5d00 (h23 ep1in [1/0] q1 p1) qh256-0001/f68e5e00 (h24 ep1in [1/0]
> q1 p1) qh256-0001/f543f580 (h37 ep1in [1/0] q1 p1) qh256-0001/f68e5980 (h44
> ep1in [2/0] q1 p64) qh256-0001/f68e5780 (h45 ep1in [2/0] q1 p64)
> qh256-0001/f68e5700 (h46 ep1in [2/0] q1 p64) qh256-0001/f68e5680 (h47 ep1in
> [2/0] q1 p64) qh256-0001/f68e5900 (h48 ep1in [2/0] q1 p64) qh256-0001/f68e5880
> (h49 ep1in [2/0] q1 p64) qh256-0001/f68e5800 (h50 ep1in [2/0] q1 p64)
> qh256-0001/f68e5400 (h51 ep1in [2/0] q1 p64) qh256-0001/f68e5380 (h52 ep1in
> [2/0] q1 p64) qh256-0001/f68e5300 (h53 ep1in [2/0] q1 p64) qh256-0001/f68e5280
> (h54 ep1in [2/0] q1 p64) qh256-0001/f68e5200 (h55 ep1in [2/0] q1 p64)
> qh256-0001/f68e5180 (h56 ep1in [2/0] q1 p64) qh256-0001/f561c000 (h57 ep1in
> [2/0] q1 p64) qh256-0001/f561c080 (h58 ep1in [2/0] q1 p64) qh256-0001/f561c100
> (h59 ep1in [2/0] q1 p64) qh256-0001/f561c180 (h60 ep1in [2/0] q1 p64)
> qh256-0001/f561c200 (h61 ep1in [2/0] q1 p64) qh256-0001/f561c280 (h62 ep1in
> [2/0] q1 p64) qh256-0001/f561c300 (h63 ep1in [2/0] q1 p64) qh256-0001/f561c380
> (h64 ep1in [2/0] q1 p64) qh256-0001/f561c400 (h65 ep1in [2/0] q1 p64)
> qh256-0001/f561c480 (h66 ep1in [2/0] q1 p64) qh256-0001/f561c500 (h67 ep1in
> [2/0] q1 p64) qh256-0001/f561c580 (h68 ep1in [2/0] q1 p64) qh256-0001/f561c600
> (h69 ep1in [2/0] q1 p64) qh256-0001/f561c680 (h70 ep1in [2/0] q1 p64)
> qh256-0001/f561c700 (h71 ep1in [2/0] q1 p64) qh256-0001/f561c780 (h72 ep1in
> [2/0] q1 p64) qh256-0001/f561c800 (h73 ep1in [2/0] q1 p64) qh256-0001/f561c880
> (h74 ep1in [2/0] q1 p64) qh256-0001/f561c900 (h75 ep1in [2/0] q1 p64)
> qh256-0001/f561c980 (h76 ep1in [2/0] q1 p64) qh256-0001/f561ca00 (h77 ep1in
> [2/0] q1 p64) qh256-0001/f561ca80 (h78 ep1in [2/0] q1 p64) qh256-0001/f561cb00
> (h79 ep1in [2/0] q1 p64)
> >
> >
> > Maybe a USB scheduler bug is causing them to all be queued for the same
> > microframe?
>
> No, it's not a bug -- it was my oversight. I didn't notice that the
> scheduler tries to put all interrupt transfers as early as possible.
> There's no particular reason for this as far as I can see; that was
> just the easiest way to do it.
>
> The patch below will cause things to be more spread out. You won't
> even have to include the 1-ms delays in your driver!
>
> Alan Stern
>
>
> Index: usb-2.6/drivers/usb/host/ehci-sched.c
> ===================================================================
> --- usb-2.6.orig/drivers/usb/host/ehci-sched.c
> +++ usb-2.6/drivers/usb/host/ehci-sched.c
> @@ -760,8 +760,10 @@ static int qh_schedule(struct ehci_hcd *
> if (status) {
> /* "normal" case, uframing flexible except with splits */
> if (qh->period) {
> - frame = qh->period - 1;
> - do {
> + int i;
> +
> + for (i = qh->period; status && i > 0; --i) {
> + frame = ++ehci->random_frame % qh->period;
> for (uframe = 0; uframe < 8; uframe++) {
> status = check_intr_schedule (ehci,
> frame, uframe, qh,
> @@ -769,7 +771,7 @@ static int qh_schedule(struct ehci_hcd *
> if (status == 0)
> break;
> }
> - } while (status && frame--);
> + }
>
> /* qh->period == 0 means every uframe */
> } else {
> Index: usb-2.6/drivers/usb/host/ehci.h
> ===================================================================
> --- usb-2.6.orig/drivers/usb/host/ehci.h
> +++ usb-2.6/drivers/usb/host/ehci.h
> @@ -116,6 +116,7 @@ struct ehci_hcd { /* one per controlle
> struct timer_list watchdog;
> unsigned long actions;
> unsigned stamp;
> + unsigned random_frame;
> unsigned long next_statechange;
> u32 command;
Yes! It works! :-D
Thank you.
Now the periodic schedule looks like this:
size = 256
1: qh256-0001/f68e5100 (h2 ep1in [1/0] q1 p1)
2: qh256-0001/f68e5500 (h9 ep1in [1/0] q1 p1)
3: qh256-0001/f68e5600 (h10 ep1in [1/0] q1 p1)
4: qh256-0001/f68e5d00 (h23 ep1in [1/0] q1 p1)
5: qh256-0001/f68e5e00 (h24 ep1in [1/0] q1 p1)
6: qh256-0001/f5de5580 (h37 ep1in [1/0] q1 p1)
7: qh256-0001/f68e5980 (h44 ep1in [2/0] q1 p64)
8: qh256-0001/f68e5900 (h45 ep1in [2/0] q1 p64)
9: qh256-0001/f68e5880 (h46 ep1in [2/0] q1 p64)
10: qh256-0001/f68e5800 (h47 ep1in [2/0] q1 p64)
11: qh256-0001/f68e5780 (h48 ep1in [2/0] q1 p64)
12: qh256-0001/f68e5700 (h49 ep1in [2/0] q1 p64)
13: qh256-0001/f68e5680 (h50 ep1in [2/0] q1 p64)
14: qh256-0001/f68e5400 (h51 ep1in [2/0] q1 p64)
15: qh256-0001/f68e5380 (h52 ep1in [2/0] q1 p64)
16: qh256-0001/f68e5300 (h53 ep1in [2/0] q1 p64)
17: qh256-0001/f68e5280 (h54 ep1in [2/0] q1 p64)
18: qh256-0001/f68e5200 (h55 ep1in [2/0] q1 p64)
19: qh256-0001/f68e5180 (h56 ep1in [2/0] q1 p64)
20: qh256-0001/f5795000 (h57 ep1in [2/0] q1 p64)
21: qh256-0001/f5795080 (h58 ep1in [2/0] q1 p64)
22: qh256-0001/f5795100 (h59 ep1in [2/0] q1 p64)
23: qh256-0001/f5795180 (h60 ep1in [2/0] q1 p64)
24: qh256-0001/f5795200 (h61 ep1in [2/0] q1 p64)
25: qh256-0001/f5795280 (h62 ep1in [2/0] q1 p64)
26: qh256-0001/f5795300 (h63 ep1in [2/0] q1 p64)
27: qh256-0001/f5795380 (h64 ep1in [2/0] q1 p64)
28: qh256-0001/f5795400 (h65 ep1in [2/0] q1 p64)
29: qh256-0001/f5795480 (h66 ep1in [2/0] q1 p64)
30: qh256-0001/f5795500 (h67 ep1in [2/0] q1 p64)
31: qh256-0001/f5795580 (h68 ep1in [2/0] q1 p64)
32: qh256-0001/f5795600 (h69 ep1in [2/0] q1 p64)
33: qh256-0001/f5795680 (h70 ep1in [2/0] q1 p64)
34: qh256-0001/f5795700 (h71 ep1in [2/0] q1 p64)
35: qh256-0001/f5795780 (h72 ep1in [2/0] q1 p64)
36: qh256-0001/f5795800 (h73 ep1in [2/0] q1 p64)
37: qh256-0001/f5795880 (h74 ep1in [2/0] q1 p64)
38: qh256-0001/f5795900 (h75 ep1in [2/0] q1 p64)
39: qh256-0001/f5795980 (h76 ep1in [2/0] q1 p64)
40: qh256-0001/f5795a00 (h77 ep1in [2/0] q1 p64)
41: qh256-0001/f5795a80 (h78 ep1in [2/0] q1 p64)
42: qh256-0001/f5795b00 (h79 ep1in [2/0] q1 p64)
and I get 36 interrupt transfers:
f56a4080 1207844021 C Ii:065:01 0 24 = aa55aa55 00000010 23000002 1002d0e1 00000183 00000000
f56a4080 1207844033 S Ii:065:01 -115 32 <
f56a5780 1208080951 C Ii:046:01 0 24 = aa55aa55 00000010 23000002 1002d0e1 00000295 00000000
f56a5780 1208080962 S Ii:046:01 -115 32 <
f5682400 1208081944 C Ii:047:01 0 24 = aa55aa55 00000010 23000002 1002d0e1 0000011b 00000000
f5682400 1208081954 S Ii:047:01 -115 32 <
f5684880 1208082944 C Ii:048:01 0 24 = aa55aa55 00000010 23000002 1002d0e1 0000011c 00000000
f5684880 1208082955 S Ii:048:01 -115 32 <
f5679780 1208083943 C Ii:049:01 0 24 = aa55aa55 00000010 23000002 1002d0e1 00000254 00000000
f5679780 1208083952 S Ii:049:01 -115 32 <
f5518200 1208084944 C Ii:050:01 0 24 = aa55aa55 00000010 23000002 1002d0e1 000000ec 00000000
f5518200 1208084954 S Ii:050:01 -115 32 <
f7384500 1208085943 C Ii:051:01 0 24 = aa55aa55 00000010 23000002 1002d0e1 000002d6 00000000
f7384500 1208085952 S Ii:051:01 -115 32 <
f55e4a80 1208088944 C Ii:054:01 0 24 = aa55aa55 00000010 23000002 1002d0e1 000000f1 00000000
f55e4a80 1208088953 S Ii:054:01 -115 32 <
f56a5500 1208089942 C Ii:055:01 0 24 = aa55aa55 00000010 23000002 1002d0e1 0000023c 00000000
f56a5500 1208089950 S Ii:055:01 -115 32 <
f5684000 1208090942 C Ii:056:01 0 24 = aa55aa55 00000010 23000002 1002d0e1 000002bd 00000000
f5684000 1208090952 S Ii:056:01 -115 32 <
f552f480 1208091940 C Ii:057:01 0 24 = aa55aa55 00000010 23000002 1002d0e1 00000167 00000000
f552f480 1208091949 S Ii:057:01 -115 32 <
f5684900 1208095942 C Ii:061:01 0 24 = aa55aa55 00000010 23000002 1002d0e1 000000ca 00000000
f5684900 1208095952 S Ii:061:01 -115 32 <
f6b7b080 1208096940 C Ii:062:01 0 24 = aa55aa55 00000010 23000002 1002d0e1 00000213 00000000
f6b7b080 1208096950 S Ii:062:01 -115 32 <
f55e4d80 1208097938 C Ii:063:01 0 24 = aa55aa55 00000010 23000002 1002d0e1 00000271 00000000
f55e4d80 1208097948 S Ii:063:01 -115 32 <
f5646500 1208100940 C Ii:066:01 0 24 = aa55aa55 00000010 23000002 1002d0e1 00000132 00000000
f5646500 1208100949 S Ii:066:01 -115 32 <
f567b400 1208101940 C Ii:067:01 0 24 = aa55aa55 00000010 23000002 1002d0e1 000000b8 00000000
f567b400 1208101950 S Ii:067:01 -115 32 <
f5e7f100 1208103939 C Ii:069:01 0 24 = aa55aa55 00000010 23000002 1002d0e1 00000096 00000000
f5e7f100 1208103948 S Ii:069:01 -115 32 <
f6947980 1208104939 C Ii:070:01 0 24 = aa55aa55 00000010 23000002 1002d0e1 0000006a 00000000
f6947980 1208104949 S Ii:070:01 -115 32 <
f5d01a00 1208106938 C Ii:072:01 0 24 = aa55aa55 00000010 23000002 1002d0e1 000000af 00000000
f5d01a00 1208106948 S Ii:072:01 -115 32 <
f552ff80 1208107936 C Ii:073:01 0 24 = aa55aa55 00000010 23000002 1002d0e1 0000010e 00000000
f552ff80 1208107946 S Ii:073:01 -115 32 <
f56b7380 1208108937 C Ii:074:01 0 24 = aa55aa55 00000010 23000002 1002d0e1 00000219 00000000
f56b7380 1208108946 S Ii:074:01 -115 32 <
f5684300 1208109937 C Ii:075:01 0 24 = aa55aa55 00000010 23000002 1002d0e1 00000118 00000000
f5684300 1208109947 S Ii:075:01 -115 32 <
f5646280 1208110936 C Ii:076:01 0 24 = aa55aa55 00000010 23000002 1002d0e1 00000207 00000000
f5646280 1208110945 S Ii:076:01 -115 32 <
f55f4300 1208111937 C Ii:077:01 0 24 = aa55aa55 00000010 23000002 1002d0e1 00000115 00000000
f55f4300 1208111946 S Ii:077:01 -115 32 <
f56a4900 1208112936 C Ii:078:01 0 24 = aa55aa55 00000010 23000002 1002d0e1 000000dd 00000000
f56a4900 1208112945 S Ii:078:01 -115 32 <
f4406680 1208113936 C Ii:079:01 0 24 = aa55aa55 00000010 23000002 1002d0e1 00000180 00000000
f4406680 1208113946 S Ii:079:01 -115 32 <
f5e7fc80 1208334883 C Ii:044:01 0 24 = aa55aa55 00000010 23000002 1002d0e1 00000108 00000000
f5e7fc80 1208334891 S Ii:044:01 -115 32 <
f55e4180 1208335878 C Ii:045:01 0 24 = aa55aa55 00000010 23000002 1002d0e1 0000011e 00000000
f55e4180 1208335888 S Ii:045:01 -115 32 <
f56a4880 1208342879 C Ii:052:01 0 24 = aa55aa55 00000010 23000002 1002d0e1 0000017f 00000000
f56a4880 1208342888 S Ii:052:01 -115 32 <
f56b7900 1208343876 C Ii:053:01 0 24 = aa55aa55 00000010 23000002 1002d0e1 0000018b 00000000
f56b7900 1208343886 S Ii:053:01 -115 32 <
f5682200 1208348877 C Ii:058:01 0 24 = aa55aa55 00000010 23000002 1002d0e1 0000020c 00000000
f5682200 1208348886 S Ii:058:01 -115 32 <
f6968300 1208349874 C Ii:059:01 0 24 = aa55aa55 00000010 23000002 1002d0e1 00000142 00000000
f6968300 1208349883 S Ii:059:01 -115 32 <
f55fe100 1208350874 C Ii:060:01 0 24 = aa55aa55 00000010 23000002 1002d0e1 00000211 00000000
f55fe100 1208350884 S Ii:060:01 -115 32 <
f5679900 1208354875 C Ii:064:01 0 24 = aa55aa55 00000010 23000002 1002d0e1 00000186 00000000
f5679900 1208354883 S Ii:064:01 -115 32 <
f56b7d00 1208358874 C Ii:068:01 0 24 = aa55aa55 00000010 23000002 1002d0e1 000000b4 00000000
f56b7d00 1208358884 S Ii:068:01 -115 32 <
f5684b00 1208361873 C Ii:071:01 0 24 = aa55aa55 00000010 23000002 1002d0e1 00000126 00000000
f5684b00 1208361882 S Ii:071:01 -115 32 <
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