Dave: While working on this, I noticed there's still no code in ehci-q.c to handle Clear-TT-Buffer for ARC/TDI embedded TTs. Looking through the Freescale MCIMX31 and Intel IXP45X manuals explained why -- both of them say (in the "Asynchronous Transaction Scheduling and Buffer Management" section of the "EHCI Deviation" subchapter): Clear_TT_Buffer capability provided though the use of the ___ register. It sure looks like something was meant to be filled in there but never made it. Similarly, the "Operational Registers" section under "EHCI Deviation" says: The following additions have been added to the operational registers to support the embedded TT: A new register. Addition of two-bit Port Speed (PSPD) to the PORTSCx register. Well, the PSPD bits are documented, but there don't seem to be any new operational registers related to the embedded TT. So what's the story? Does anybody know how this is implemented, or even if it is implemented at all? Is there somebody at Freescale or Intel we can ask about it? Alan Stern -- To unsubscribe from this list: send the line "unsubscribe linux-usb" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
