On Mon, May 6, 2019 at 6:47 PM Chris Brandt <chris.brandt@xxxxxxxxxxx> wrote: > > Document the optional renesas,uses_usb_x1 property. > > Signed-off-by: Chris Brandt <chris.brandt@xxxxxxxxxxx> > --- > Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt > index d46188f450bf..26bf377102d3 100644 > --- a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt > +++ b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt > @@ -46,6 +46,8 @@ channel as USB OTG: > regulator will be managed during the PHY power on/off sequence. > - renesas,no-otg-pins: boolean, specify when a board does not provide proper > otg pins. > +- renesas,use_usb_x1: boolean, the dedicated 48MHz crystal inputs USB_X1 are > + used for the PLL source s/_/-/
