Re: [PATCH 2/5] usb: dwc2: Move phy init into core

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Hi Jules,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on balbi-usb/next]
[also build test ERROR on v5.1-rc3 next-20190402]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Jules-Maselbas/usb-dwc2-Improve-gadget-phy-init/20190403-103251
base:   https://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git next
config: i386-randconfig-l1-04030817 (attached as .config)
compiler: gcc-5 (Debian 5.5.0-3) 5.4.1 20171010
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

All errors (new ones prefixed by >>):

   drivers/usb/dwc2/hcd.c: In function 'dwc2_core_host_init':
>> drivers/usb/dwc2/hcd.c:2185:2: error: implicit declaration of function 'dwc2_init_fs_ls_pclk_sel' [-Werror=implicit-function-declaration]
     dwc2_init_fs_ls_pclk_sel(hsotg);
     ^
   cc1: some warnings being treated as errors

vim +/dwc2_init_fs_ls_pclk_sel +2185 drivers/usb/dwc2/hcd.c

b02038fa John Youn         2016-02-23  2152  
b02038fa John Youn         2016-02-23  2153  /**
b02038fa John Youn         2016-02-23  2154   * dwc2_core_host_init() - Initializes the DWC_otg controller registers for
b02038fa John Youn         2016-02-23  2155   * Host mode
b02038fa John Youn         2016-02-23  2156   *
b02038fa John Youn         2016-02-23  2157   * @hsotg: Programming view of DWC_otg controller
b02038fa John Youn         2016-02-23  2158   *
b02038fa John Youn         2016-02-23  2159   * This function flushes the Tx and Rx FIFOs and flushes any entries in the
b02038fa John Youn         2016-02-23  2160   * request queues. Host channels are reset to ensure that they are ready for
b02038fa John Youn         2016-02-23  2161   * performing transfers.
b02038fa John Youn         2016-02-23  2162   */
b02038fa John Youn         2016-02-23  2163  static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
b02038fa John Youn         2016-02-23  2164  {
92a8dd26 Minas Harutyunyan 2018-01-19  2165  	u32 hcfg, hfir, otgctl, usbcfg;
b02038fa John Youn         2016-02-23  2166  
b02038fa John Youn         2016-02-23  2167  	dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
b02038fa John Youn         2016-02-23  2168  
92a8dd26 Minas Harutyunyan 2018-01-19  2169  	/* Set HS/FS Timeout Calibration to 7 (max available value).
92a8dd26 Minas Harutyunyan 2018-01-19  2170  	 * The number of PHY clocks that the application programs in
92a8dd26 Minas Harutyunyan 2018-01-19  2171  	 * this field is added to the high/full speed interpacket timeout
92a8dd26 Minas Harutyunyan 2018-01-19  2172  	 * duration in the core to account for any additional delays
92a8dd26 Minas Harutyunyan 2018-01-19  2173  	 * introduced by the PHY. This can be required, because the delay
92a8dd26 Minas Harutyunyan 2018-01-19  2174  	 * introduced by the PHY in generating the linestate condition
92a8dd26 Minas Harutyunyan 2018-01-19  2175  	 * can vary from one PHY to another.
92a8dd26 Minas Harutyunyan 2018-01-19  2176  	 */
f25c42b8 Gevorg Sahakyan   2018-07-26  2177  	usbcfg = dwc2_readl(hsotg, GUSBCFG);
92a8dd26 Minas Harutyunyan 2018-01-19  2178  	usbcfg |= GUSBCFG_TOUTCAL(7);
f25c42b8 Gevorg Sahakyan   2018-07-26  2179  	dwc2_writel(hsotg, usbcfg, GUSBCFG);
92a8dd26 Minas Harutyunyan 2018-01-19  2180  
b02038fa John Youn         2016-02-23  2181  	/* Restart the Phy Clock */
f25c42b8 Gevorg Sahakyan   2018-07-26  2182  	dwc2_writel(hsotg, 0, PCGCTL);
b02038fa John Youn         2016-02-23  2183  
b02038fa John Youn         2016-02-23  2184  	/* Initialize Host Configuration Register */
b02038fa John Youn         2016-02-23 @2185  	dwc2_init_fs_ls_pclk_sel(hsotg);
38e9002b Vardan Mikayelyan 2016-11-14  2186  	if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
38e9002b Vardan Mikayelyan 2016-11-14  2187  	    hsotg->params.speed == DWC2_SPEED_PARAM_LOW) {
f25c42b8 Gevorg Sahakyan   2018-07-26  2188  		hcfg = dwc2_readl(hsotg, HCFG);
b02038fa John Youn         2016-02-23  2189  		hcfg |= HCFG_FSLSSUPP;
f25c42b8 Gevorg Sahakyan   2018-07-26  2190  		dwc2_writel(hsotg, hcfg, HCFG);
b02038fa John Youn         2016-02-23  2191  	}
b02038fa John Youn         2016-02-23  2192  
b02038fa John Youn         2016-02-23  2193  	/*
b02038fa John Youn         2016-02-23  2194  	 * This bit allows dynamic reloading of the HFIR register during
b02038fa John Youn         2016-02-23  2195  	 * runtime. This bit needs to be programmed during initial configuration
b02038fa John Youn         2016-02-23  2196  	 * and its value must not be changed during runtime.
b02038fa John Youn         2016-02-23  2197  	 */
95832c00 John Youn         2017-01-23  2198  	if (hsotg->params.reload_ctl) {
f25c42b8 Gevorg Sahakyan   2018-07-26  2199  		hfir = dwc2_readl(hsotg, HFIR);
b02038fa John Youn         2016-02-23  2200  		hfir |= HFIR_RLDCTRL;
f25c42b8 Gevorg Sahakyan   2018-07-26  2201  		dwc2_writel(hsotg, hfir, HFIR);
b02038fa John Youn         2016-02-23  2202  	}
b02038fa John Youn         2016-02-23  2203  
95832c00 John Youn         2017-01-23  2204  	if (hsotg->params.dma_desc_enable) {
b02038fa John Youn         2016-02-23  2205  		u32 op_mode = hsotg->hw_params.op_mode;
b02038fa John Youn         2016-02-23  2206  
b02038fa John Youn         2016-02-23  2207  		if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a ||
b02038fa John Youn         2016-02-23  2208  		    !hsotg->hw_params.dma_desc_enable ||
b02038fa John Youn         2016-02-23  2209  		    op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
b02038fa John Youn         2016-02-23  2210  		    op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
b02038fa John Youn         2016-02-23  2211  		    op_mode == GHWCFG2_OP_MODE_UNDEFINED) {
b02038fa John Youn         2016-02-23  2212  			dev_err(hsotg->dev,
b02038fa John Youn         2016-02-23  2213  				"Hardware does not support descriptor DMA mode -\n");
b02038fa John Youn         2016-02-23  2214  			dev_err(hsotg->dev,
b02038fa John Youn         2016-02-23  2215  				"falling back to buffer DMA mode.\n");
95832c00 John Youn         2017-01-23  2216  			hsotg->params.dma_desc_enable = false;
b02038fa John Youn         2016-02-23  2217  		} else {
f25c42b8 Gevorg Sahakyan   2018-07-26  2218  			hcfg = dwc2_readl(hsotg, HCFG);
b02038fa John Youn         2016-02-23  2219  			hcfg |= HCFG_DESCDMA;
f25c42b8 Gevorg Sahakyan   2018-07-26  2220  			dwc2_writel(hsotg, hcfg, HCFG);
b02038fa John Youn         2016-02-23  2221  		}
b02038fa John Youn         2016-02-23  2222  	}
b02038fa John Youn         2016-02-23  2223  
b02038fa John Youn         2016-02-23  2224  	/* Configure data FIFO sizes */
b02038fa John Youn         2016-02-23  2225  	dwc2_config_fifos(hsotg);
b02038fa John Youn         2016-02-23  2226  
b02038fa John Youn         2016-02-23  2227  	/* TODO - check this */
b02038fa John Youn         2016-02-23  2228  	/* Clear Host Set HNP Enable in the OTG Control Register */
f25c42b8 Gevorg Sahakyan   2018-07-26  2229  	otgctl = dwc2_readl(hsotg, GOTGCTL);
b02038fa John Youn         2016-02-23  2230  	otgctl &= ~GOTGCTL_HSTSETHNPEN;
f25c42b8 Gevorg Sahakyan   2018-07-26  2231  	dwc2_writel(hsotg, otgctl, GOTGCTL);
b02038fa John Youn         2016-02-23  2232  
b02038fa John Youn         2016-02-23  2233  	/* Make sure the FIFOs are flushed */
b02038fa John Youn         2016-02-23  2234  	dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */);
b02038fa John Youn         2016-02-23  2235  	dwc2_flush_rx_fifo(hsotg);
b02038fa John Youn         2016-02-23  2236  
b02038fa John Youn         2016-02-23  2237  	/* Clear Host Set HNP Enable in the OTG Control Register */
f25c42b8 Gevorg Sahakyan   2018-07-26  2238  	otgctl = dwc2_readl(hsotg, GOTGCTL);
b02038fa John Youn         2016-02-23  2239  	otgctl &= ~GOTGCTL_HSTSETHNPEN;
f25c42b8 Gevorg Sahakyan   2018-07-26  2240  	dwc2_writel(hsotg, otgctl, GOTGCTL);
b02038fa John Youn         2016-02-23  2241  
95832c00 John Youn         2017-01-23  2242  	if (!hsotg->params.dma_desc_enable) {
b02038fa John Youn         2016-02-23  2243  		int num_channels, i;
b02038fa John Youn         2016-02-23  2244  		u32 hcchar;
b02038fa John Youn         2016-02-23  2245  
b02038fa John Youn         2016-02-23  2246  		/* Flush out any leftover queued requests */
bea8e86c John Youn         2016-11-03  2247  		num_channels = hsotg->params.host_channels;
b02038fa John Youn         2016-02-23  2248  		for (i = 0; i < num_channels; i++) {
f25c42b8 Gevorg Sahakyan   2018-07-26  2249  			hcchar = dwc2_readl(hsotg, HCCHAR(i));
b02038fa John Youn         2016-02-23  2250  			hcchar &= ~HCCHAR_CHENA;
b02038fa John Youn         2016-02-23  2251  			hcchar |= HCCHAR_CHDIS;
b02038fa John Youn         2016-02-23  2252  			hcchar &= ~HCCHAR_EPDIR;
f25c42b8 Gevorg Sahakyan   2018-07-26  2253  			dwc2_writel(hsotg, hcchar, HCCHAR(i));
b02038fa John Youn         2016-02-23  2254  		}
b02038fa John Youn         2016-02-23  2255  
b02038fa John Youn         2016-02-23  2256  		/* Halt all channels to put them into a known state */
b02038fa John Youn         2016-02-23  2257  		for (i = 0; i < num_channels; i++) {
f25c42b8 Gevorg Sahakyan   2018-07-26  2258  			hcchar = dwc2_readl(hsotg, HCCHAR(i));
b02038fa John Youn         2016-02-23  2259  			hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS;
b02038fa John Youn         2016-02-23  2260  			hcchar &= ~HCCHAR_EPDIR;
f25c42b8 Gevorg Sahakyan   2018-07-26  2261  			dwc2_writel(hsotg, hcchar, HCCHAR(i));
b02038fa John Youn         2016-02-23  2262  			dev_dbg(hsotg->dev, "%s: Halt channel %d\n",
b02038fa John Youn         2016-02-23  2263  				__func__, i);
79d6b8c5 Sevak Arakelyan   2018-01-19  2264  
79d6b8c5 Sevak Arakelyan   2018-01-19  2265  			if (dwc2_hsotg_wait_bit_clear(hsotg, HCCHAR(i),
79d6b8c5 Sevak Arakelyan   2018-01-19  2266  						      HCCHAR_CHENA, 1000)) {
79d6b8c5 Sevak Arakelyan   2018-01-19  2267  				dev_warn(hsotg->dev, "Unable to clear enable on channel %d\n",
b02038fa John Youn         2016-02-23  2268  					 i);
b02038fa John Youn         2016-02-23  2269  			}
b02038fa John Youn         2016-02-23  2270  		}
b02038fa John Youn         2016-02-23  2271  	}
b02038fa John Youn         2016-02-23  2272  
66e77a24 Razmik Karapetyan 2018-01-24  2273  	/* Enable ACG feature in host mode, if supported */
66e77a24 Razmik Karapetyan 2018-01-24  2274  	dwc2_enable_acg(hsotg);
66e77a24 Razmik Karapetyan 2018-01-24  2275  
b02038fa John Youn         2016-02-23  2276  	/* Turn on the vbus power */
b02038fa John Youn         2016-02-23  2277  	dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state);
b02038fa John Youn         2016-02-23  2278  	if (hsotg->op_state == OTG_STATE_A_HOST) {
b02038fa John Youn         2016-02-23  2279  		u32 hprt0 = dwc2_read_hprt0(hsotg);
b02038fa John Youn         2016-02-23  2280  
b02038fa John Youn         2016-02-23  2281  		dev_dbg(hsotg->dev, "Init: Power Port (%d)\n",
b02038fa John Youn         2016-02-23  2282  			!!(hprt0 & HPRT0_PWR));
b02038fa John Youn         2016-02-23  2283  		if (!(hprt0 & HPRT0_PWR)) {
b02038fa John Youn         2016-02-23  2284  			hprt0 |= HPRT0_PWR;
f25c42b8 Gevorg Sahakyan   2018-07-26  2285  			dwc2_writel(hsotg, hprt0, HPRT0);
b02038fa John Youn         2016-02-23  2286  		}
b02038fa John Youn         2016-02-23  2287  	}
b02038fa John Youn         2016-02-23  2288  
b02038fa John Youn         2016-02-23  2289  	dwc2_enable_host_interrupts(hsotg);
b02038fa John Youn         2016-02-23  2290  }
b02038fa John Youn         2016-02-23  2291  

:::::: The code at line 2185 was first introduced by commit
:::::: b02038faa7f1b228983d05633c8345f826b20042 usb: dwc2: Move host-specific core functions into hcd.c

:::::: TO: John Youn <johnyoun@xxxxxxxxxxxx>
:::::: CC: Felipe Balbi <balbi@xxxxxxxxxx>

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0-DAY kernel test infrastructure                Open Source Technology Center
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