Re: Mass Storage Gadget Device Falls from SuperSpeed to High Speed

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Hi Rob,

Felipe Balbi <felipe.balbi@xxxxxxxxxxxxxxx> writes:
>>> modphy is the USB PHY integrated in your SoC. There's no control for
>>> that from OS side, only BIOS unfortunately. There is, however, one thing
>>> we can try. DWC3 has several quirk flags for known quirky PHYs; perhaps
>>> CHT needs one of those. Can you try with this patch and let me know
>>> whether it helps?
>>
>> Sure thing, I will try tomorrow. Could you possibly explain what a quirk
>> is as it relates to the kernel? I see this all over the source tree but
>> never knew how it was used. Does the dwc3 also know about "quirks" and
>> these particular flags? or are these flags just specific to the kernel
>> and its functionality?
>>
>>> modified   drivers/usb/dwc3/dwc3-pci.c
>>> @@ -105,6 +105,8 @@ static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci)
>>>  static const struct property_entry dwc3_pci_intel_properties[] = {
>>>  	PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
>>>  	PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
>>> +	PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
>>> +	PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
>>>  	{}
>>>  };
>>>  
>>> These two quirks will PHY suspend. There are other relevant quirk flags
>                     ^^^^^^^^
>                     will DISABLE phy suspend :-)
>
>> What do you mean by PHY suspend? Will it disable U2/U3 for the dwc3? I
>
> No, no. DWC3 can still enter U1/U2/U3, but the PHY will not enter the
> matching P1/P2/P3 state.
>
>> see it modified the DWC3_GUSB2PHYCFG_SUSPHY bit in the configuration
>> register, but I don't have access to the dwc3 databook to dig deeper
>> into this.
>
> The second quirk flag (snps,dis_u2_susphy_quirk) will tell dwc3 to *NOT*
> request USB2 PHY to enter low power state. While the first flag
> (snps,dis_u3_susphy_quirk) will tell dwc3 to *NOT* request USB3 PHY to
> enter low power state.
>
> In reality, they are a single block of HW but they _can_ be different
> and even if they are a single block, they _can_ have separate clock
> domains and we _may_ be able to control them separately. I haven't read
> documentation for modphy because the OS doesn't touch that. If
> necessary, I can try to find out more details about it, but I will
> probably take some time to find the correct documentation.
>
>>> which we can try in case these two don't help. I'd like to figure out
>>> exactly which quirk flag helps (if any). After that, we would need to
>>> check if a similar problem happens on any CHT system or just your
>>> design.
>>> 
>>> If it happens on any other system, then I can make sure we add a quirk
>>> flag to all CHTs.
>>
>> Sounds good!
>>
>> Thanks for taking the time to answer my questions! It's definitely
>> helpful for my understanding of USB. I'm learning quite a bit of
>> new information with each email and it's pretty awesome.
>
> No problems at all, happy to help.

Any updates here? Hopefully the quirk flags above helped.

-- 
balbi

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