Hi,
On 18/03/2019 20:57, Martin Blumenstingl wrote:
> Hi Neil,
>
> On Mon, Mar 18, 2019 at 2:29 PM Neil Armstrong <narmstrong@xxxxxxxxxxxx> wrote:
>>
>> Adds support for Amlogic G12A USB Control Glue HW.
>>
>> The Amlogic G12A SoC Family embeds 2 USB Controllers :
>> - a DWC3 IP configured as Host for USB2 and USB3
>> - a DWC2 IP configured as Peripheral USB2 Only
>>
>> A glue connects these both controllers to 2 USB2 PHYs, and optionnally
>> to an USB3+PCIE Combo PHY shared with the PCIE controller.
>>
>> The Glue configures the UTMI 8bit interfaces for the USB2 PHYs, including
>> routing of the OTG PHY between the DWC3 and DWC2 controllers, and
>> setups the on-chip OTG mode selection for this PHY.
>>
>> This drivers supports the on-probe setup of the OTG mode, and manually
>> via a debugfs interface. The IRQ mode change detect is yet to be added
>> in a future patchset, mainly due to lack of hardware to validate on.
>>
>> Signed-off-by: Neil Armstrong <narmstrong@xxxxxxxxxxxx>
> with the small issue fixed (see below) you can add my:
> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@xxxxxxxxxxxxxx>
>
> my opinion is that the whole driver is looking great now!
> I hope that it will be queued for v5.2 soon because there's no NACK
> from the USB / dwc3 maintainers yet.
Thanks ! I will add this tag for v5 with these fixes
>
> [...]
>> + ret = of_platform_populate(np, NULL, NULL, dev);
>> + if (ret) {
>> + clk_disable_unprepare(priv->clk);
>> + clk_put(priv->clk);
> clk_disable_unprepare is called automatically since there's now an
> devm_add_action_or_reset for that a few lines above
> clk_put is also unnecessary because priv->clk is obtained with devm_clk_get()
Chunfeng Yun also reported thos on v3...
I will fix on v4 next week to give a little more time
>
>
> Regards
> Martin
>
Neil
