On 06/03/2019 22:04, Martin Blumenstingl wrote:
> Hi Neil,
>
> On Mon, Mar 4, 2019 at 11:40 AM Neil Armstrong <narmstrong@xxxxxxxxxxxx> wrote:
> [...]
>> +static int phy_g12a_usb3_init(struct phy *phy)
>> +{
>> + struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
>> + int data, ret;
>> +
>> + /* Switch PHY to USB3 */
>> + regmap_update_bits(priv->regmap, PHY_R0,
>> + PHY_R0_PCIE_USB3_SWITCH,
>> + PHY_R0_PCIE_USB3_SWITCH);
> does this automatically clear PHY_R0_PCIE_POWER_STATE (in case the
> bootloader incorrectly set that)?
Don't forget it's a static configuration, on the board, only USB3 XOR PCIE
will be available, if the bootloader sets this and the kernel uses USB3,
or the reverse, one of them is wrong.
>
> [...]
>> +static int phy_g12a_usb3_pcie_init(struct phy *phy)
>> +{
>> + struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
>> + int ret;
>> +
>> + ret = reset_control_reset(priv->reset);
>> + if (ret)
>> + return ret;
>> +
>> + if (priv->mode == PHY_TYPE_USB3)
>> + return phy_g12a_usb3_init(phy);
>> +
>> + /* Power UP PCIE */
>> + regmap_update_bits(priv->regmap, PHY_R0,
>> + PHY_R0_PCIE_POWER_STATE,
>> + FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1c));
> similar to my question above: does this automatically clear
> PHY_R0_PCIE_USB3_SWITCH (in case the bootloader incorrectly set that)?
Same answer, but I'll investigate to have more details on this register.
It's more an implementation issue, we can change it when PCIe is enabled
on this platform.
>
> Apart from these two questions this looks good to me!
Thanks for the review !
Neil
>
>
> Regards
> Martin
>
