On some Bay Trail (BYT) systems the firmware does not enable the
ULPI Refclk.
This commit adds a helper which checks and if necessary enabled the Refclk
and calls this helper for BYT machines.
Signed-off-by: Hans de Goede <hdegoede@xxxxxxxxxx>
---
drivers/usb/dwc3/dwc3-pci.c | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
index 34b84d3bc7cf..65bc110388f3 100644
--- a/drivers/usb/dwc3/dwc3-pci.c
+++ b/drivers/usb/dwc3/dwc3-pci.c
@@ -42,6 +42,9 @@
#define PCI_INTEL_BXT_STATE_D0 0
#define PCI_INTEL_BXT_STATE_D3 3
+#define GP_RWREG1 0xa0
+#define GP_RWREG1_ULPI_REFCLK_DISABLE (1 << 17)
+
/**
* struct dwc3_pci - Driver private structure
* @dwc3: child dwc3 platform_device
@@ -78,6 +81,34 @@ static struct gpiod_lookup_table platform_bytcr_gpios = {
},
};
+static void dwc3_pci_enable_ulpi_refclock(struct pci_dev *pci)
+{
+ void __iomem *reg;
+ struct resource res;
+ struct device *dev = &pci->dev;
+ u32 value;
+
+ res.start = pci_resource_start(pci, 1);
+ res.end = pci_resource_end(pci, 1);
+ res.name = "dwc_usb3_bar1";
+ res.flags = IORESOURCE_MEM;
+
+ reg = devm_ioremap_resource(dev, &res);
+ if (IS_ERR(reg)) {
+ dev_err(dev, "cannot check GP_RWREG1 to assert ulpi refclock\n");
+ return;
+ }
+
+ value = readl(reg + GP_RWREG1);
+ if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE))
+ return; /* ULPI refclk already enabled */
+
+ dev_warn(dev, "ULPI refclock is disabled from the BIOS, enabling it\n");
+ value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE;
+ writel(value, reg + GP_RWREG1);
+ msleep(100);
+}
+
static int dwc3_pci_quirks(struct dwc3_pci *dwc)
{
struct platform_device *dwc3 = dwc->dwc3;
@@ -134,6 +165,9 @@ static int dwc3_pci_quirks(struct dwc3_pci *dwc)
struct gpio_desc *gpio;
const char *vendor;
+ /* On BYT the FW does not always enable the refclock */
+ dwc3_pci_enable_ulpi_refclock(pdev);
+
ret = devm_acpi_dev_add_driver_gpios(&pdev->dev,
acpi_dwc3_byt_gpios);
if (ret)
--
2.17.1
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