Hi Felipe, On 3/14/2018 1:56 AM, Felipe Balbi wrote: > > Hi, > > Thinh Nguyen <Thinh.Nguyen@xxxxxxxxxxxx> writes: >>> Thinh Nguyen <Thinh.Nguyen@xxxxxxxxxxxx> writes: >>>> In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed >>>> isochronous IN, BIT[15:14] of the 16-bit microframe number reported by >>>> the XferNotReady event are invalid. The driver uses this number to >>>> schedule the isochronous transfer and passes it to the START TRANSFER >>>> command. Because this number is invalid, the command may fail. If >>>> BIT[15:14] matches the internal 16-bit microframe, the START TRANSFER >>>> command will pass and the transfer will start at the scheduled time, if >>>> it is off by 1, the command will still pass, but the transfer will start >>>> 2 seconds in the future. All other conditions the START TRANSFER command >>>> will fail with bus-expiry. >>>> >>>> In order to workaround this issue, we can issue multiple START TRANSFER >>>> commands with different values of BIT[15:14]: 'b00, 'b01, 'b10, and 'b11 >>>> and do an END TRANSFER command. Each combination is 2 seconds apart. 4 >>>> seconds into the future will cause a bus-expiry failure. As the result, >>>> within the 4 possible combinations for BIT[15:14], there will be 2 >>>> successful and 2 failure START COMMAND status. One of the 2 successful >>>> command status will result in a 2-second delay. The smaller BIT[15:14] >>>> value is the correct one. >>>> >>>> Since there are only 4 outcomes and the results are ordered, we can >>>> simply test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 >>>> and 'b01 to deduce the smallest successful combination. >>>> >>>> +---------+---------+ >>>> | BIT(15) | BIT(14) | >>>> +=========+=========+ >>>> test0 | 0 | 0 | >>>> +---------+---------+ >>>> test1 | 0 | 1 | >>>> +---------+---------+ >>>> >>>> With test0 and test1 BIT[15:14] combinations, here is the logic: >>>> if test0 passes and test1 passes, BIT[15:14] is 'b00 >>>> if test0 passes and test1 fails, BIT[15:14] is 'b11 >>>> if test0 fails and test1 fails, BIT[15:14] is 'b10 >>>> if test0 fails and test1 passes, BIT[15:14] is 'b01 >>>> >>>> Synopsys STAR 9001202023: Wrong microframe number for isochronous IN >>>> endpoints. >>>> >>>> Signed-off-by: Thinh Nguyen <thinhn@xxxxxxxxxxxx> >>>> --- >>>> drivers/usb/dwc3/core.c | 2 + >>>> drivers/usb/dwc3/core.h | 13 ++++ >>>> drivers/usb/dwc3/gadget.c | 189 ++++++++++++++++++++++++++++++++++++++++++++-- >>>> 3 files changed, 199 insertions(+), 5 deletions(-) >>>> >>>> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c >>>> index ddcfa2a60d4b..d27ddfcc3b8a 100644 >>>> --- a/drivers/usb/dwc3/core.c >>>> +++ b/drivers/usb/dwc3/core.c >>> >>> ... because all these tests could be combined in a simple place and >>> moved inside dwc3_set_isoc_start_frame() so that you could >>> unconditionally call it here. >>> >>> I'll go ahead and drop this series from this merge window, it clearly >>> needs much more work. >>> >> >> Thank you for reviewing the patches. I'll make the change to this patch >> for the next merge window. However, can you cherry-pick the other >> patches in this series for this merge window? If they also need more >> work, please let me know. > > I don't think it makes sense to pick the others without this, specially > since you're touching usb core on patch 2 and I can't apply that. I did, > however, take Mass Storage patch setting its max speed to SSP. > The patch to the usb core is unrelated to this workaround. Only 3 of the patches are related to the workaround. Other updates are independent of it. The ones that are related are marked with 'X' in the list below: Thinh Nguyen (15): usb: dwc3: Add SoftReset PHY synchonization delay usb: core: urb: Check SSP isoc ep comp descriptor usb: dwc3: Update DWC_usb31 GTXFIFOSIZ reg fields usb: dwc3: Check IP revision for GTXFIFOSIZ usb: dwc3: Add DWC_usb31 GRXTHRCFG bit fields usb: dwc3: gadget: Check IP revision for GRXTHRCFG usb: dwc3: Add DWC_usb31 GTXTHRCFG reg fields usb: dwc3: Make TX/RX threshold configurable usb: dwc3: Check for ESS TX/RX threshold config usb: dwc3: Dump LSP and BMU debug info X usb: dwc3: Track DWC_usb31 VERSIONTYPE X usb: dwc3: Add disabling of start_transfer failure quirk X usb: dwc3: Add workaround for isoc start transfer failure usb: dwc3: Check controller type before setting speed usb: gadget: mass_storage: Set max_speed to SSP It would be great if you can apply them this merge window. Thank you! Thinh -- To unsubscribe from this list: send the line "unsubscribe linux-usb" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
