Hi Minas,
Am 07.12.2017 um 17:51 schrieb Stefan Wahren:
Hi Minas,
Am 07.12.2017 um 09:40 schrieb Stefan Wahren:
Before flushing fifos required to check AHB master state and
flush when AHB master is in IDLE state.
Signed-off-by: Minas Harutyunyan <hminas@xxxxxxxxxxxx>
---
drivers/usb/dwc2/core.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c
index dbca3b8890da..cbc7c562477f 100644
--- a/drivers/usb/dwc2/core.c
+++ b/drivers/usb/dwc2/core.c
@@ -670,10 +670,23 @@ void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num)
dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num);
+ /* Wait for AHB master IDLE state */
+ do {
+ udelay(1);
is this delay always necessary before reading GRSTCTL?
If yes please add a comment why.
If no please rework the loop in order to avoid this delay in case the
AHB master is already idle.
i've seen your Patch V2, but it isn't what i thought of. How about:
while (1) {
greset = dwc2_readl(hsotg->regs + GRSTCTL);
if (greset & GRSTCTL_AHBIDLE)
break;
if (++count > 10000) {
dev_warn(hsotg->dev,
"%s() HANG! AHB Idle GRSTCTL=%0x\n",
__func__, greset);
return;
}
}
Btw: Please provide a change history, so the maintainers can keep track
of your changes.
Regards
Stefan
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