Re: VL805 xHCI DMA read faults

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On 09/10/17 10:22, Mathias Nyman wrote:
> On 08.10.2017 17:03, Hao Wei Tee wrote:
>> Hi,
>>
>> I've been having DMA read faults with my VL805 xHCI controller when
>> the Intel IOMMU
>> is turned on:
>>
>>      xhci_hcd 0000:03:00.0: xHCI Host Controller
>>      xhci_hcd 0000:03:00.0: new USB bus registered, assigned bus number 2
>>      DMAR: DRHD: handling fault status reg 3
>>      DMAR: [DMA Read] Request device [03:00.0] fault addr de28a000
>> [fault reason 01] Present bit in root entry is clear
>>      <snip many identical DMAR faults>
>>      xhci_hcd 0000:03:00.0: can't setup: -110
>>      xhci_hcd 0000:03:00.0: USB bus 2 deregistered
>>      xhci_hcd 0000:03:00.0: init 0000:03:00.0 fail, -110
>>      xhci_hcd: probe of 0000:03:00.0 failed with error -110
>>
>> The controller works fine, as far as I can tell, when the IOMMU is off.
>>
>> I've tracked it down to where CMD_RESET is sent to the controller in
>> xhci_reset,
>> [1] called from xhci_gen_setup in xhci.c. It seems that when the
>> command register
>> is being polled in the xhci_handshake after that, the controller tries
>> to do a
>> DMA read from an address that is apparently invalid (?). Eventually
>> xhci_handshake
>> times out.
>>
>> I've tried setting the XHCI_NO_64BIT_SUPPORT quirks flag as someone
>> suggested in
>> an earlier thread here [2] about a similar/the same(?) device, but
>> that doesn't
>> seem to have worked.
>>
>> Help, please. I have no idea how to debug this further.
>>
> 
> Could it maybe be related to a iommu/vt-d: Fix scatterlist offset
> handling fix:
> https://lists.linuxfoundation.org/pipermail/iommu/2017-September/024371.html
> 
> 
> Can you check if that patch is included?
> 
> The author Robin Murphy (CC) Also had some recent issues with a VIA
> VL805 controller
> 
> https://marc.info/?l=linux-usb&m=150730678304383&w=2

I'm pretty confident this is unrelated to the intel-iommu issue that
my patch above addresses. On my arm64 test system, the VL805 is
consistently playing up even *without* an IOMMU - dd'ing from a USB3
mass storage device throws up a series of block layer errors like this:

[  138.658733] sd 2:0:0:0: [sdb] tag#0 UNKNOWN(0x2003) Result: hostbyte=0x07 driverbyte=0x00
[  138.666853] sd 2:0:0:0: [sdb] tag#0 CDB: opcode=0x28 28 00 00 00 00 a8 00 01 80 00
[  138.674369] print_req_error: I/O error, dev sdb, sector 168


Brain dump so far:

 - I can reliably produce these errors using dd with a block size of
   128K or greater; more generally they seem correlated with
   dma_map_sg() calls where the scatterlist is 32 or more entries long.

 - without the IOMMU, block sizes >=128K all settle down into a
   suspiciously-periodic error every 2048 sectors.

 - with the IOMMU, the faulting write address is always the first byte
   of a page immediately following a valid XHCI DMA mapping; I'm no USB
   expert, but having now generated the debug log below, this might
   actually just be a symptom of the queue getting out of whack earlier.

 - FWIW, neither XHCI_NO_64BIT_SUPPORT as mentioned in the other thread,
   nor XHCI_BROKEN_STREAMS per the other VIA quirk, makes any visible
   difference.

 - The same device works quite happily in USB 2.0 ports on the same
   system (via on-SoC EHCI), and with a different USB 3.0 PCIe card
   based on a Renesas uPD720201.

Robin.


--->8---
This is the IOMMU-enabled version of everything from the point of
plugging in my USB3/SATA adapter to the out-of-bounds write that
triggers a fault (from which the host controller then never really
recovers):

[  425.195232] xhci_hcd 0000:04:00.0: Port Status Change Event for port 1
[  425.201708] xhci_hcd 0000:04:00.0: resume root hub
[  425.206459] xhci_hcd 0000:04:00.0: port resume event for port 1
[  425.212324] xhci_hcd 0000:04:00.0: resume HS port 1
[  425.217158] xhci_hcd 0000:04:00.0: handle_port_status: starting port polling.
[  425.224299] xhci_hcd 0000:04:00.0: get port status, actual port 0 status  = 0x40000fe3
[  425.232140] xhci_hcd 0000:04:00.0: Get port status returned 0x507
[  425.238285] xhci_hcd 0000:04:00.0: suspend failed because a port is resuming
[  425.245299] xhci_hcd 0000:04:00.0: Resume USB2 port 1
[  425.250723] xhci_hcd 0000:04:00.0: Port Status Change Event for port 1
[  425.257243] xhci_hcd 0000:04:00.0: get port status, actual port 0 status  = 0x40000fe3
[  425.265084] xhci_hcd 0000:04:00.0: Get port status returned 0x40503
[  425.271351] xhci_hcd 0000:04:00.0: get port status, actual port 0 status  = 0x40400e03
[  425.279192] xhci_hcd 0000:04:00.0: Get port status returned 0x40503
[  425.285469] xhci_hcd 0000:04:00.0: clear port suspend/resume change, actual port 0 status  = 0x40000e03
[  425.312450] xhci_hcd 0000:04:00.0: get port status, actual port 0 status  = 0x40000e03
[  425.320292] xhci_hcd 0000:04:00.0: Get port status returned 0x503
[  425.356419] xhci_hcd 0000:04:00.0: xhci_hub_status_data: stopping port polling.
[  425.436469] xhci_hcd 0000:04:00.0: get port status, actual port 0 status  = 0x40000e03
[  425.444311] xhci_hcd 0000:04:00.0: Get port status returned 0x503
[  425.450412] xhci_hcd 0000:04:00.0: Cancel URB ffff800059170700, dev 1, ep 0x81, starting at offset 0xfff50010
[  425.460239] xhci_hcd 0000:04:00.0: // Ding dong!
[  425.465277] xhci_hcd 0000:04:00.0: Stopped on Transfer TRB for slot 1 ep 2
[  425.472093] xhci_hcd 0000:04:00.0: Removing canceled TD starting at 0xfff50010 (dma).
[  425.479849] xhci_hcd 0000:04:00.0: Finding endpoint context
[  425.485368] xhci_hcd 0000:04:00.0: Cycle state = 0x1
[  425.490284] xhci_hcd 0000:04:00.0: New dequeue segment = ffff800052667180 (virtual)
[  425.497867] xhci_hcd 0000:04:00.0: New dequeue pointer = 0xfff50020 (DMA)
[  425.504594] xhci_hcd 0000:04:00.0: Set TR Deq Ptr cmd, new deq seg = ffff800052667180 (0xfff50000 dma), new deq ptr = ffff00000aafd020 (0xfff50020 dma), new cycle = 1
[  425.519315] xhci_hcd 0000:04:00.0: // Ding dong!
[  425.523960] xhci_hcd 0000:04:00.0: Successful Set TR Deq Ptr cmd, deq = @fff50020
[  425.531586] xhci_hcd 0000:04:00.0: // Ding dong!
[  425.536267] xhci_hcd 0000:04:00.0: Stopped on No-op or Link TRB for slot 1 ep 0
[  425.580463] xhci_hcd 0000:04:00.0: xhci_hub_status_data: stopping port polling.
[  425.685717] xhci_hcd 0000:04:00.0: Port Status Change Event for port 1
[  425.692184] xhci_hcd 0000:04:00.0: resume root hub
[  425.696934] xhci_hcd 0000:04:00.0: port resume event for port 1
[  425.702798] xhci_hcd 0000:04:00.0: resume HS port 1
[  425.707630] xhci_hcd 0000:04:00.0: handle_port_status: starting port polling.
[  425.714750] xhci_hcd 0000:04:00.0: get port status, actual port 0 status  = 0x40000fe3
[  425.722591] xhci_hcd 0000:04:00.0: Get port status returned 0x507
[  425.728655] xhci_hcd 0000:04:00.0: Port Status Change Event for port 5
[  425.735127] xhci_hcd 0000:04:00.0: resume root hub
[  425.739872] xhci_hcd 0000:04:00.0: handle_port_status: starting port polling.
[  425.747051] xhci_hcd 0000:04:00.0: get port status, actual port 0 status  = 0x2a0
[  425.754462] xhci_hcd 0000:04:00.0: Get port status returned 0x2a0
[  425.760554] xhci_hcd 0000:04:00.0: get port status, actual port 1 status  = 0x2a0
[  425.767965] xhci_hcd 0000:04:00.0: Get port status returned 0x2a0
[  425.774051] xhci_hcd 0000:04:00.0: get port status, actual port 2 status  = 0x2a0
[  425.781461] xhci_hcd 0000:04:00.0: Get port status returned 0x2a0
[  425.787542] xhci_hcd 0000:04:00.0: get port status, actual port 3 status  = 0x21203
[  425.795124] xhci_hcd 0000:04:00.0: Get port status returned 0x10203
[  425.801386] xhci_hcd 0000:04:00.0: clear port connect change, actual port 3 status  = 0x1203
[  425.809796] xhci_hcd 0000:04:00.0: Resume USB2 port 1
[  425.815280] xhci_hcd 0000:04:00.0: Port Status Change Event for port 1
[  425.821783] xhci_hcd 0000:04:00.0: get port status, actual port 0 status  = 0x40000fe3
[  425.829624] xhci_hcd 0000:04:00.0: Get port status returned 0x40503
[  425.835889] xhci_hcd 0000:04:00.0: clear port suspend/resume change, actual port 0 status  = 0x40000e03
[  425.852413] xhci_hcd 0000:04:00.0: xhci_hub_status_data: stopping port polling.
[  425.859670] xhci_hcd 0000:04:00.0: xhci_hub_status_data: stopping port polling.
[  425.866949] xhci_hcd 0000:04:00.0: get port status, actual port 0 status  = 0x40000e03
[  425.874790] xhci_hcd 0000:04:00.0: Get port status returned 0x503
[  425.916452] xhci_hcd 0000:04:00.0: get port status, actual port 3 status  = 0x1203
[  425.923950] xhci_hcd 0000:04:00.0: Get port status returned 0x203
[  425.930027] xhci_hcd 0000:04:00.0: xhci_hub_status_data: stopping port polling.
[  425.937345] xhci_hcd 0000:04:00.0: // Ding dong!
[  425.942030] xhci_hcd 0000:04:00.0: Slot 2 output ctx = 0xff367000 (dma)
[  425.948629] xhci_hcd 0000:04:00.0: Slot 2 input ctx = 0xfef68000 (dma)
[  425.955175] xhci_hcd 0000:04:00.0: Set slot id 2 dcbaa entry ffff00000a88e010 to 0xff367000
[  425.963495] xhci_hcd 0000:04:00.0: get port status, actual port 3 status  = 0x1203
[  425.970992] xhci_hcd 0000:04:00.0: Get port status returned 0x203
[  425.977084] xhci_hcd 0000:04:00.0: set port reset, actual port 3 status  = 0x311
[  425.984434] xhci_hcd 0000:04:00.0: Port Status Change Event for port 5
[  425.990901] xhci_hcd 0000:04:00.0: handle_port_status: starting port polling.
[  425.998126] xhci_hcd 0000:04:00.0: Cancel URB ffff800059170700, dev 1, ep 0x81, starting at offset 0xfff50020
[  426.007950] xhci_hcd 0000:04:00.0: // Ding dong!
[  426.012979] xhci_hcd 0000:04:00.0: Stopped on Transfer TRB for slot 1 ep 2
[  426.019793] xhci_hcd 0000:04:00.0: Removing canceled TD starting at 0xfff50020 (dma).
[  426.027548] xhci_hcd 0000:04:00.0: Finding endpoint context
[  426.033067] xhci_hcd 0000:04:00.0: Cycle state = 0x1
[  426.037983] xhci_hcd 0000:04:00.0: New dequeue segment = ffff800052667180 (virtual)
[  426.045565] xhci_hcd 0000:04:00.0: New dequeue pointer = 0xfff50030 (DMA)
[  426.052291] xhci_hcd 0000:04:00.0: Set TR Deq Ptr cmd, new deq seg = ffff800052667180 (0xfff50000 dma), new deq ptr = ffff00000aafd030 (0xfff50030 dma), new cycle = 1
[  426.067012] xhci_hcd 0000:04:00.0: // Ding dong!
[  426.071656] xhci_hcd 0000:04:00.0: Successful Set TR Deq Ptr cmd, deq = @fff50030
[  426.079129] xhci_hcd 0000:04:00.0: get port status, actual port 3 status  = 0x201203
[  426.086798] xhci_hcd 0000:04:00.0: Get port status returned 0x100203
[  426.093193] xhci_hcd 0000:04:00.0: clear port reset change, actual port 3 status  = 0x1203
[  426.101429] xhci_hcd 0000:04:00.0: xhci_hub_status_data: stopping port polling.
[  426.108715] xhci_hcd 0000:04:00.0: // Ding dong!
[  426.113350] xhci_hcd 0000:04:00.0: clear port warm(BH) reset change, actual port 3 status  = 0x1203
[  426.122335] xhci_hcd 0000:04:00.0: Stopped on No-op or Link TRB for slot 1 ep 0
[  426.129659] xhci_hcd 0000:04:00.0: clear port link state change, actual port 3 status  = 0x1203
[  426.138322] xhci_hcd 0000:04:00.0: clear port connect change, actual port 3 status  = 0x1203
[  426.146727] xhci_hcd 0000:04:00.0: get port status, actual port 3 status  = 0x1203
[  426.154224] xhci_hcd 0000:04:00.0: Get port status returned 0x203
[  426.176456] xhci_hcd 0000:04:00.0: xhci_hub_status_data: stopping port polling.
[  426.216438] xhci_hcd 0000:04:00.0: Set root hub portnum to 5
[  426.222062] xhci_hcd 0000:04:00.0: Set fake root hub portnum to 4
[  426.228122] xhci_hcd 0000:04:00.0: udev->tt =           (null)
[  426.233924] xhci_hcd 0000:04:00.0: udev->ttport = 0x0
[  426.238956] xhci_hcd 0000:04:00.0: // Ding dong!
[  426.243802] xhci_hcd 0000:04:00.0: Successful setup address command
[  426.250036] xhci_hcd 0000:04:00.0: Op regs DCBAA ptr = 0x000000ffec6000
[  426.256611] xhci_hcd 0000:04:00.0: Slot ID 2 dcbaa entry @ffff00000a88e010 = 0x000000ff367000
[  426.265080] xhci_hcd 0000:04:00.0: Output Context DMA address = 0xff367000
[  426.271911] xhci_hcd 0000:04:00.0: Internal device address = 0
[  426.277721] xhci_hcd 0000:04:00.0: Endpoint 0x0 ep reset callback called
[  426.284382] usb 4-4: new SuperSpeed USB device number 2 using xhci_hcd
[  426.309422] xhci_hcd 0000:04:00.0: Waiting for status stage event
[  426.315652] xhci_hcd 0000:04:00.0: Waiting for status stage event
[  426.321847] xhci_hcd 0000:04:00.0: Waiting for status stage event
[  426.328156] xhci_hcd 0000:04:00.0: Waiting for status stage event
[  426.334673] xhci_hcd 0000:04:00.0: add ep 0x83, slot id 2, new drop flags = 0x0, new add flags = 0x80
[  426.343883] xhci_hcd 0000:04:00.0: add ep 0xa, slot id 2, new drop flags = 0x0, new add flags = 0x100080
[  426.353387] xhci_hcd 0000:04:00.0: xhci_check_bandwidth called for udev ffff800066df1000
[  426.361437] xhci_hcd 0000:04:00.0: // Ding dong!
[  426.366418] xhci_hcd 0000:04:00.0: Successful Endpoint Configure command
[  426.373086] xhci_hcd 0000:04:00.0: Endpoint 0x83 ep reset callback called
[  426.379842] xhci_hcd 0000:04:00.0: Endpoint 0xa ep reset callback called
[  426.386836] usb-storage 4-4:1.0: USB Mass Storage device detected
[  426.393312] scsi host2: usb-storage 4-4:1.0
[  427.425331] scsi 2:0:0:0: Direct-Access     TS1GSDOM 22V              0309 PQ: 0 ANSI: 6
[  427.434163] sd 2:0:0:0: [sdb] 1981727 512-byte logical blocks: (1.01 GB/968 MiB)
[  427.442166] sd 2:0:0:0: [sdb] Write Protect is off
[  427.446947] sd 2:0:0:0: [sdb] Mode Sense: 1f 00 10 08
[  427.452631] sd 2:0:0:0: [sdb] Write cache: enabled, read cache: enabled, supports DPO and FUA
[  427.480264] Alternate GPT is invalid, using primary GPT.
[  427.485572]  sdb: sdb1
[  427.490033] sd 2:0:0:0: [sdb] Attached SCSI disk
[  427.507512] xhci_hcd 0000:04:00.0: ep 0x83 - asked for 96 bytes, 74 bytes untransferred
[  427.515449] xhci_hcd 0000:04:00.0: Giveback URB ffff800059248400, len = 22, expected = 96, status = 0
[  427.524788] xhci_hcd 0000:04:00.0: Stalled endpoint for slot 2 ep 6
[  427.531008] xhci_hcd 0000:04:00.0: Cleaning up stalled endpoint ring
[  427.537301] xhci_hcd 0000:04:00.0: Finding endpoint context
[  427.542820] xhci_hcd 0000:04:00.0: Cycle state = 0x1
[  427.547737] xhci_hcd 0000:04:00.0: New dequeue segment = ffff80006a320200 (virtual)
[  427.555319] xhci_hcd 0000:04:00.0: New dequeue pointer = 0xff0b06e0 (DMA)
[  427.562041] xhci_hcd 0000:04:00.0: Queueing new dequeue state
[  427.567735] xhci_hcd 0000:04:00.0: Set TR Deq Ptr cmd, new deq seg = ffff80006a320200 (0xff0b0000 dma), new deq ptr = ffff00000ab4d6e0 (0xff0b06e0 dma), new cycle = 1
[  427.582456] xhci_hcd 0000:04:00.0: // Ding dong!
[  427.587032] xhci_hcd 0000:04:00.0: Giveback URB ffff8000524a3a00, len = 0, expected = 13, status = -32
[  427.596259] xhci_hcd 0000:04:00.0: Ignoring reset ep completion code of 1
[  427.602986] xhci_hcd 0000:04:00.0: Successful Set TR Deq Ptr cmd, deq = @ff0b06e0
[  427.610604] xhci_hcd 0000:04:00.0: Endpoint 0x83 ep reset callback called
[  427.682231] xhci_hcd 0000:04:00.0: Stalled endpoint for slot 2 ep 6
[  427.688454] xhci_hcd 0000:04:00.0: Cleaning up stalled endpoint ring
[  427.694748] xhci_hcd 0000:04:00.0: Finding endpoint context
[  427.700267] xhci_hcd 0000:04:00.0: Cycle state = 0x1
[  427.705183] xhci_hcd 0000:04:00.0: New dequeue segment = ffff80006a320200 (virtual)
[  427.712766] xhci_hcd 0000:04:00.0: New dequeue pointer = 0xff0b0b60 (DMA)
[  427.719488] xhci_hcd 0000:04:00.0: Queueing new dequeue state
[  427.725183] xhci_hcd 0000:04:00.0: Set TR Deq Ptr cmd, new deq seg = ffff80006a320200 (0xff0b0000 dma), new deq ptr = ffff00000ab4db60 (0xff0b0b60 dma), new cycle = 1
[  427.739904] xhci_hcd 0000:04:00.0: // Ding dong!
[  427.744480] xhci_hcd 0000:04:00.0: Giveback URB ffff800059248400, len = 65536, expected = 196608, status = -32
[  427.754455] xhci_hcd 0000:04:00.0: Ignoring reset ep completion code of 1
[  427.761183] xhci_hcd 0000:04:00.0: Successful Set TR Deq Ptr cmd, deq = @ff0b0b60
[  427.768783] xhci_hcd 0000:04:00.0: Endpoint 0x83 ep reset callback called
[  427.804718] xhci_hcd 0000:04:00.0: Stalled endpoint for slot 2 ep 6
[  427.810934] xhci_hcd 0000:04:00.0: Cleaning up stalled endpoint ring
[  427.817226] xhci_hcd 0000:04:00.0: Finding endpoint context
[  427.822745] xhci_hcd 0000:04:00.0: Cycle state = 0x1
[  427.827661] xhci_hcd 0000:04:00.0: New dequeue segment = ffff80006a320200 (virtual)
[  427.835243] xhci_hcd 0000:04:00.0: New dequeue pointer = 0xff0b0bd0 (DMA)
[  427.841965] xhci_hcd 0000:04:00.0: Queueing new dequeue state
[  427.847659] xhci_hcd 0000:04:00.0: Set TR Deq Ptr cmd, new deq seg = ffff80006a320200 (0xff0b0000 dma), new deq ptr = ffff00000ab4dbd0 (0xff0b0bd0 dma), new cycle = 1
[  427.862380] xhci_hcd 0000:04:00.0: // Ding dong!
[  427.866956] xhci_hcd 0000:04:00.0: Giveback URB ffff800052696e00, len = 65536, expected = 196608, status = -32
[  427.876931] xhci_hcd 0000:04:00.0: Ignoring reset ep completion code of 1
[  427.883659] xhci_hcd 0000:04:00.0: Successful Set TR Deq Ptr cmd, deq = @ff0b0bd0
[  427.891189] xhci_hcd 0000:04:00.0: Endpoint 0x83 ep reset callback called
[  427.928710] xhci_hcd 0000:04:00.0: Stalled endpoint for slot 2 ep 6
[  427.934925] xhci_hcd 0000:04:00.0: Cleaning up stalled endpoint ring
[  427.941218] xhci_hcd 0000:04:00.0: Finding endpoint context
[  427.946737] xhci_hcd 0000:04:00.0: Cycle state = 0x1
[  427.951654] xhci_hcd 0000:04:00.0: New dequeue segment = ffff80006a320200 (virtual)
[  427.959235] xhci_hcd 0000:04:00.0: New dequeue pointer = 0xff0b0c40 (DMA)
[  427.965957] xhci_hcd 0000:04:00.0: Queueing new dequeue state
[  427.971650] xhci_hcd 0000:04:00.0: Set TR Deq Ptr cmd, new deq seg = ffff80006a320200 (0xff0b0000 dma), new deq ptr = ffff00000ab4dc40 (0xff0b0c40 dma), new cycle = 1
[  427.986371] xhci_hcd 0000:04:00.0: // Ding dong!
[  427.990947] xhci_hcd 0000:04:00.0: Giveback URB ffff80004f1bf900, len = 65536, expected = 196608, status = -32
[  428.000923] xhci_hcd 0000:04:00.0: Ignoring reset ep completion code of 1
[  428.007650] xhci_hcd 0000:04:00.0: Successful Set TR Deq Ptr cmd, deq = @ff0b0c40
[  428.015178] xhci_hcd 0000:04:00.0: Endpoint 0x83 ep reset callback called
[  428.052714] xhci_hcd 0000:04:00.0: Stalled endpoint for slot 2 ep 6
[  428.058930] xhci_hcd 0000:04:00.0: Cleaning up stalled endpoint ring
[  428.065223] xhci_hcd 0000:04:00.0: Finding endpoint context
[  428.070741] xhci_hcd 0000:04:00.0: Cycle state = 0x1
[  428.075658] xhci_hcd 0000:04:00.0: New dequeue segment = ffff80006a320200 (virtual)
[  428.083240] xhci_hcd 0000:04:00.0: New dequeue pointer = 0xff0b0cb0 (DMA)
[  428.089961] xhci_hcd 0000:04:00.0: Queueing new dequeue state
[  428.095655] xhci_hcd 0000:04:00.0: Set TR Deq Ptr cmd, new deq seg = ffff80006a320200 (0xff0b0000 dma), new deq ptr = ffff00000ab4dcb0 (0xff0b0cb0 dma), new cycle = 1
[  428.110376] xhci_hcd 0000:04:00.0: // Ding dong!
[  428.114951] xhci_hcd 0000:04:00.0: Giveback URB ffff80006944d400, len = 65536, expected = 196608, status = -32
[  428.124926] xhci_hcd 0000:04:00.0: Ignoring reset ep completion code of 1
[  428.131653] xhci_hcd 0000:04:00.0: Successful Set TR Deq Ptr cmd, deq = @ff0b0cb0
[  428.139191] xhci_hcd 0000:04:00.0: Endpoint 0x83 ep reset callback called
[  428.176713] xhci_hcd 0000:04:00.0: Stalled endpoint for slot 2 ep 6
[  428.182928] xhci_hcd 0000:04:00.0: Cleaning up stalled endpoint ring
[  428.189221] xhci_hcd 0000:04:00.0: Finding endpoint context
[  428.194739] xhci_hcd 0000:04:00.0: Cycle state = 0x1
[  428.199655] xhci_hcd 0000:04:00.0: New dequeue segment = ffff80006a320200 (virtual)
[  428.207238] xhci_hcd 0000:04:00.0: New dequeue pointer = 0xff0b0d20 (DMA)
[  428.213959] xhci_hcd 0000:04:00.0: Queueing new dequeue state
[  428.219653] xhci_hcd 0000:04:00.0: Set TR Deq Ptr cmd, new deq seg = ffff80006a320200 (0xff0b0000 dma), new deq ptr = ffff00000ab4dd20 (0xff0b0d20 dma), new cycle = 1
[  428.234373] xhci_hcd 0000:04:00.0: // Ding dong!
[  428.238949] xhci_hcd 0000:04:00.0: Giveback URB ffff800059248a00, len = 65536, expected = 196608, status = -32
[  428.248921] xhci_hcd 0000:04:00.0: Ignoring reset ep completion code of 1
[  428.255648] xhci_hcd 0000:04:00.0: Successful Set TR Deq Ptr cmd, deq = @ff0b0d20
[  428.263221] xhci_hcd 0000:04:00.0: Endpoint 0x83 ep reset callback called
[  428.300711] xhci_hcd 0000:04:00.0: Stalled endpoint for slot 2 ep 6
[  428.306926] xhci_hcd 0000:04:00.0: Cleaning up stalled endpoint ring
[  428.313219] xhci_hcd 0000:04:00.0: Finding endpoint context
[  428.318738] xhci_hcd 0000:04:00.0: Cycle state = 0x1
[  428.323655] xhci_hcd 0000:04:00.0: New dequeue segment = ffff80006a320200 (virtual)
[  428.331237] xhci_hcd 0000:04:00.0: New dequeue pointer = 0xff0b0d90 (DMA)
[  428.337958] xhci_hcd 0000:04:00.0: Queueing new dequeue state
[  428.343652] xhci_hcd 0000:04:00.0: Set TR Deq Ptr cmd, new deq seg = ffff80006a320200 (0xff0b0000 dma), new deq ptr = ffff00000ab4dd90 (0xff0b0d90 dma), new cycle = 1
[  428.358373] xhci_hcd 0000:04:00.0: // Ding dong!
[  428.362949] xhci_hcd 0000:04:00.0: Giveback URB ffff800052696e00, len = 65536, expected = 196608, status = -32
[  428.372923] xhci_hcd 0000:04:00.0: Ignoring reset ep completion code of 1
[  428.379651] xhci_hcd 0000:04:00.0: Successful Set TR Deq Ptr cmd, deq = @ff0b0d90
[  428.387179] xhci_hcd 0000:04:00.0: Endpoint 0x83 ep reset callback called
[  428.394006] sd 2:0:0:0: [sdb] tag#0 UNKNOWN(0x2003) Result: hostbyte=0x07 driverbyte=0x00
[  428.402132] sd 2:0:0:0: [sdb] tag#0 CDB: opcode=0x28 28 00 00 00 00 80 00 01 80 00
[  428.409645] print_req_error: I/O error, dev sdb, sector 128
[  428.426612] arm-smmu 2b500000.iommu: Unhandled context fault: fsr=0x8, iova=0xff0b1000, fsynr=0x183, cb=0
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