Hi Frank, Am Montag, 6. Februar 2017, 09:40:35 CET schrieb Frank Wang: > On 2017/2/5 17:41, Heiko Stuebner wrote: > > Am Sonntag, 5. Februar 2017, 10:51:00 CET schrieb Frank Wang: > >> The original posting on Jan 19th have not received any responses, so I > >> resend them. > >> > >> The Current default dwc2 just handle one clock named otg, however, it may > >> have two or more clock need to manage for some new SoCs(such as RK3328), > >> so > >> this adds change clk to clk's array of dwc2_hsotg to handle more clocks > >> operation. > > > > can you please give a bit more detail on the specific layout. > > > > I guess you're talking about hclk_otg_pmu, right? What component does it > > supply, because I didn't find anything in the partial TRM in the PMU > > section relating to the "otg". > > Yes, it is hclk_otg_pmu. > > The rock-chip hclk_otg_pmu is an input clock for dwc2 PMU module which > named pmu_hclk in chapter 2.4 of dwc otg databook v3.10. ok great, on establishing that this is a actual part of the IP block. I'm going to comment on the actual code change in a minute, so see you over there :-) Heiko -- To unsubscribe from this list: send the line "unsubscribe linux-usb" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
