Vincent Pelletier <plr.vincent@xxxxxxxxx> writes: > On Mon, 23 Jan 2017 16:30:57 +0200, Felipe Balbi > <felipe.balbi@xxxxxxxxxxxxxxx> wrote: >> well, the IN limit can be lower than what HW reports depending on how >> your TX FIFO space is setup. > > And while I am in regdump, in case it would help (especially all the > GTXFIFOSIZ entries and GDBGFIFOSPACE ?) while lowering the number of > mail round-trips... thanks GHWPARAMS0 = 0x2020400a from this we get MDWIDTH = 64 / 8 = 8 GHWPARAMS7 = 0x038807e6 GTXFIFOSIZ(0) = 0x00000042 fifo_size = 0x42 * MDWIDTH - 8 - 8 = 512 *(8 and 8 are overheads, more below) GTXFIFOSIZ(1) = 0x00420184 fifo_size = (0x184 * MDWIDTH) - 8 - 8 - 8 - 8 = 3072 GTXFIFOSIZ(2) = 0x01c60184 fifo_size = 3072 GTXFIFOSIZ(3) = 0x034a0184 fifo_size = 3072 GTXFIFOSIZ(4) = 0x04ce0082 fifo_size = (0x82 * MDWIDTH) - 8 - 8 = 1024 GTXFIFOSIZ(5) = 0x05500082 fifo_size = 1024 GTXFIFOSIZ(6) = 0x05d20082 fifo_size = 1024 GTXFIFOSIZ(7) = 0x06540082 fifo_size = 1024 GTXFIFOSIZ(8) = 0x06d60022 fifo_size = 1024 GTXFIFOSIZ(9) = 0x06f80022 fifo_size = (0x22 * MDIWDTH) - 8 - 8 = 256 GTXFIFOSIZ(10) = 0x071a0022 fifo_size = 256 GTXFIFOSIZ(11) = 0x073c0022 fifo_size = 256 GTXFIFOSIZ(12) = 0x075e0022 fifo_size = 256 GTXFIFOSIZ(13) = 0x07800022 fifo_size = 256 GTXFIFOSIZ(14) = 0x07a20022 fifo_size = 256 GTXFIFOSIZ(15) = 0x07c40022 fifo_size = 256 Seems like HW engineer wanted these last few endpoints to *not* support full USB3 packets. They are probably supposed to be used for Isochronous and/or Interrupts endpoints. At some point we need to support this as well. During initialization we should read FIFO size configuration and extract wMaxPacketSize for $endpoint from the HW. * the overheads are a bit funny. IIRC (I have to confirm), you have MDWIDTH overhead for every single endpoint. Plus MDWIDTH overhead for each full packet endpoint can support. So an endpoint with 3072 byte FIFO supports 3 full 1024 byte packets. So it has MDWIDTH * 3 + MDWIDTH overhead. -- balbi
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