Re: link state problem with dwc3 in supper-speed device mode

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Hi,

Bin Liu <b-liu@xxxxxx> writes:
>> >> > There is no VBUS detection on this device and board. Is the VBUS
>> >> > detection needed for dwc3 to work in device mode? 
>> >> 
>> >> In the case of DRA7x, you don't *really* need detection. All you need to
>> >> do is correctly update UTMI mailbox.
>> >
>> > But the UTMI mailbox is driven by extcon events, right? The board
>> > doesn't have external circuit or gpio to detect VBUS.
>> 
>> Then you should use ID event to *also* fiddle with VBUSVALID bit. That
>> used to work just fine, I guess commit below broke it:
>
> I don't understand how this dra7-evm worked before. dwc3 is in SS device
> mode, microB cable does not ground ID pin, so there is ID event when
> attach/detach dwc3 to the host. I am confused...

Please read about the mailbox in your SoC. Try to figure out how it
works and what it does. What happens, internally, when you write
VBUS_VALID and/or IDGND bits. What does that mean to dwc3? When can dwc3
connect its data pullups? What information does it need in order to do
that? Many of these questions will be answered ;-)

Hint: dwc3 doesn't know about any GPIOs or VBUS comparators or whatever
you may place in the PCB. DWC3 only understands PIPE3 and
ULPI/UTMI. So how does the mailbox come in the picture? Why do we need
it? Is it replacing any other component? Which component would that be?

cheers

-- 
balbi

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