Hi, Mason <slash.tmp@xxxxxxx> writes: > Hello Felipe, > > On 30/05/2016 08:58, Felipe Balbi wrote: > >> Mason writes: >> >>> I'm working on a SoC which embeds an IP block from GDA Technologies >>> labeled "Pravega USB3 SuperSpeed Controller" (data-sheet is v0.99r >>> dated 2014-01-29). A cursory search returns: >>> >>> http://www.sourcing.co.jp/prod_ip.htm >>> http://www.sourcing.co.jp/prod_ip/usb_host_pb.pdf >>> >>> In the compliance section, the data-sheet lists: >>> >>> - USB 3.0 Revision 1.0 and all associated ECNs >>> - Inter-Chip Supplement to the USB Revision 3.0 Specification, Revision 1.02 >>> - Backward compatible with USB2.0 Revision 2.0 and all associated ECNs >>> - High Speed Inter Chip Specification, Rev 1.0 and associated ECNs >>> - USB 2.0 Link Power Management Addendum and associated Erratas >>> - xHCI specification version 1.0 (in host mode) >>> >>> My question is: should I be able to use the generic XHCI driver to >>> drive this controller? >> >> yes, you should. BUT... is this controller dual-role? If it is, then >> it'd be nice to support both roles. > > Dual-role means OTG? or just static host/device? > AFAIU, my version of the controller only supports host-mode. okay, then xhci-plat it is >>> (The Makefile builds xhci-plat-hcd.o but I don't see xhci-plat-hcd.c >>> Is it a generated file?) >> >> The makefile is smart enough to figure it out. Don't worry. Kernel's >> build system knows that it needs xhci-plat-hcd.c in order to build >> xhci-plat-hcd.o > > Oh, I wasn't worried. I was curious how/where that file is generated. alright :) >>> One more thing: AFAIU, the USB PHY is made by Synopsys. >>> Do I need a driver for that too? (I should examine 7b8ef22ea547) >> >> IIRC there are no registers to be configured on Synopsys PHY, so no. > > I looked more closely at the SoC documentation, which lists registers > such as > > 0x0 CONFIG > 0x4 CONTROL > 0x8 TEST > 0xC STATUS > 0x10 CLK_RST_0 > 0x14 CLK_RST_1 > 0x18 PARAM_0 > 0x1C PARAM_1 > 0x20 PARAM_2 > 0x80 SNPS_CR_ADD > 0x84 SNPS_CR_DATA > 0xC0 RESET_CTRL > > For example, PARAM_1 contains a field "TX De-emphasis at 6 dB". > That's PHY stuff, right? > > Are registers such as PHY_TIMER_REGISTER or LTSSM_* standard in USB3/XHCI, > or is that PHY stuff too? seems like. Okay, I'm guessing here the SoC vendor decided to expose some details in registers so they can do trimming after SoC has taped out. Normally, SNPS' PHY doesn't expose registers -- balbi
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